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參數(shù)資料
| 型號(hào)： | SM5166 |
| 廠商： | Seiko NPC Corporation |
| 英文描述： | MINIATURE POWER RELAY |
| 中文描述： | PLL合成器集成電路 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 91K |
| 代理商： | SM5166 |
SM5166AV
NIPPON PRECISION CIRCUITS—6
Input Data Format
Shift register timing
Latch select
The last (17th) data bit determines the status of the
shift register data latch.
Swallow counter and main counter frequency divider
Input data example
If the VCO output (f
frequency (f
bandwidth (f
kHz, then the comparator frequency divider ratio N
is given by:
VCO
) is trebled, the output
) is 251.3 MHz, and the channel
: operating frequency (f
LO
CH
R
)
×
3) is 25
Therefore, the swallow counter count is 4 (00100)
and the main frequency divider counter count is 314
(0000100111010)
2
. The input data format is shown
in figure 3.
2
Figure 1. Comparator data format
DATA
CLK
LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
MSB
LSB
CONTROL
Table 1. Latch select bit function
Bit 17
Latch
0
Swallow counter and main counter frequency divider
ratio latch select
1
Reference frequency counter divider ratio data and
LD output latch select
Figure 2. Swallow counter and main counter frequency divider data format
DATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
MSB
LSB
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
10
9
8
7
6
5
4
3
2
1
0
4
3
2
1
0
Main counter
(11-bit : 32 to 2047)
Swallow counter
(5-bit : 0 to 31)
Latch selection bit : Set to "0"
N
f
f
CH
---------
f
f
R
3
3
-----------------------
251.3 3
0.025 3
-------------------
10052
32
314
4
+
×
=
=
=
=
=
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