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參數(shù)資料
| 型號： | SM5842APT |
| 廠商： | Seiko NPC Corporation |
| 英文描述： | High-Class Audio Multi-function Digital Filter |
| 中文描述： | 高級音頻多功能數(shù)字濾波器 |
| 文件頁數(shù)： | 16/23頁 |
| 文件大小： | 201K |
| 代理商： | SM5842APT |
SM5842AP/APT
NIPPON PRECISION CIRCUITS—16
System Reset (RSTN)
Under
SM5842AP/APT does not need to be reset. However,
it can be reset when you want to synchronize the
LRCI clock and internal operation timing in jitter-
free mode.
normal
operating
conditions,
the
The system is reset by applying a LOW-level pulse
on RSTN.
The arithmetic and output timing counters are reset
on the first LRCI start edge after reset is released, as
long as the XTI clock has already stabilized. The
LRCI start edge is determined by the state of INF1N
and INF2N. When INF1N is LOW or when both
INF1N and INF2N are HIGH, the start edge is the
rising edge. When INF1N is HIGH and INF2N is
LOW, the start edge is the falling edge.
When RSTN is LOW, the DOL and DOR outputs are
LOW, muting the output signal to an attenuation
level of
∞
.
The power-ON reset pulse can be applied by a
microcontroller or, for systems where XTI and LRCI
are stable at power-ON, by connecting a capacitor of
about 300 pF between RSTN and VSS. For systems
that do not use a microcontroller, the capacitor must
be chosen such that the XTI and LRCI clocks fully
stabilize before RSTN goes from LOW to HIGH.
Figure 3. System reset timing and output muting
RSTN
LRCI
DOL
DOR
1
2
Internal reset
WCKO
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