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參數(shù)資料
| 型號(hào)： | SM5844AF |
| 廠商： | Seiko NPC Corporation |
| 英文描述： | Asynchronous Sample Rate Converter |
| 中文描述： | 異步采樣率轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 13/26頁(yè) |
| 文件大小： | 280K |
| 代理商： | SM5844AF |
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SM5844AF
NIPPON PRECISION CIRCUITS—13
Microcontroller Interface (MCOM, MDT, MCK, MLEN)
When MCOM is HIGH, MDT (data), MCK (clock)
and MLEN (latch enable clock) interface pins are
used.
Input data on MDT is synchronized to the MCK
clock. Data is read into the input stage shift register
on the rising edge of MCK. Accordingly, the input
data should change on the falling edge of MCK.
Input data enters an internal SIPO (serial-to-parallel
converter register), and then the parallel data is
latched into the mode register on the rising edge of
the latch enable clock MLEN.
The mode register addressed is determined by the 1st
bit of the 12 data bits before MLEN goes HIGH. If
this bit is LOW, then the data is read into the
attenuation data register as shown in figure 1. If this
bit is HIGH, then the data is read into the mode flag
register as shown in figure 2. The function of each bit
in the mode flag register is described in table 1.
Figure 1. Attenuation data format (B1 = LOW)
Figure 2. Mode flag data format (B1 = HIGH)
MCK
MDT
MLEN
MCK and MLEN can also follow the dotted lines.
LOW
B1
a0
B2
a1
B3
a2
B4
a6
B8
a7
B9
a8
B10
MSB
a9
B11
a10
B12
LSB
MCK
MDT
MLEN
MCK and MLEN can also follow the dotted lines.
HIGH
B1
B2
Not used
B5
FTST1
B6
FRATE
B8
F12DB
B9
FFSI1
B10
FFSI2
B11
FDEEM
B12
* *
B7
FTST2
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