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參數(shù)資料
| 型號(hào)： | SM5877 |
| 廠商： | Seiko NPC Corporation |
| 英文描述： | 3rd-order , 2-channel D/A Converter |
| 中文描述： | 第三階，2通道D / A轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大小： | 140K |
| 代理商： | SM5877 |
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SM5877AM
NIPPON PRECISION CIRCUITS—13
FUNCTIONAL DESCRIPTION
System Clock/Speed Switching (XTI, XTO, CKO, DS)
The system clock on XTI can be set to run at one of
two speeds, 384fs (normal speed) or 192fs (double-
speed), where fs is the input frequency on LRCI. The
speed for CD playback is set by the input level on
DS, as shown in table 1. The system clock should be
fixed at 16.9344 MHz.
Note that the input clock accuracy and signal-to-
noise ratio greatly influence the AC analog character-
istics. Accordingly, care should be taken to ensure
that the clock is free from jitter.
The system clock can be controlled by a crystal
oscillator comprising a crystal connected between
XTI and XTO and the built-in CMOS inverter. Alter-
natively, an external system clock can be input on
XTI. As the internal CMOS inverter has a feedback
resistor, the external clock can be AC coupled to
XTI. The system clock is output on CKO.
System Reset (RSTN)
The device should be reset in the following cases.
I
At power ON
I
When LRCI and/or the system clock XTI stop, or
other abnormalities occur.
Table 1. System clock select
Parameter
Symbol
DS
LOW
(normal
speed)
HIGH
(double
speed)
XTI input clock
frequency
f
XI
(= 1/t
XI
)
384fs
192fs
CD playback
XTI frequency
f
XI
16.9344 MHz
at fs = 44.1
kHz
16.9344 MHz
at fs = 88.2
kHz
CKO output
clock frequency
f
CO
384fs
192fs
Internal system
clock period
T
SYS
t
XI
t
XI
The device is reset by applying a LOW-level pulse on
RSTN. At system reset, the internal arithmetic opera-
tion and output timing counter are synchronized on
the next LRCI rising edge, as shown in figure 1.
Audio Data Input (DI, BCKI, LRCI)
The digital audio data is input on DI in MSB-first, 2s-
complement, 16-bit serial format.
Serial data bits are read into the SIPO register (serial-
to-parallel converter register) on the rising edge of the
bit clock BCKI.
The arithmetic operation and output timing are inde-
pendent of the input timing. Accordingly, after a reset,
Figure 1. System reset timing
RSTN
Internal reset
LO
Outputs muted
RO
LRCI
LOW
1
2
3
9
10
as long as the clock frequency ratio between LRCI
and the system clock XTI is maintained, phase dif-
ferences between LRCI, BCKI and the system clock
XTI do not affect the functional operation. Also, any
jitter present on the data input clock does not appear
as output pulse jitter.
The bit clock frequency on BCKI should be between
32fs and 64fs.
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| SM5877AM | 3rd-order , 2-channel D/A Converter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SM5877AM | 制造商:NPC 制造商全稱(chēng):Nippon Precision Circuits Inc 功能描述:3rd-order , 2-channel D/A Converter |
| SM5878 | 制造商:NPC 制造商全稱(chēng):Nippon Precision Circuits Inc 功能描述:3rd-order , 2-channel D/A converter |
| SM5878AM | 制造商:NPC 制造商全稱(chēng):Nippon Precision Circuits Inc 功能描述:3rd-order , 2-channel D/A converter |
| SM5878AV | 制造商:NPC 制造商全稱(chēng):Nippon Precision Circuits Inc 功能描述:3rd-order , 2-channel D/A converter |
| SM5879 | 制造商:NPC 制造商全稱(chēng):Nippon Precision Circuits Inc 功能描述:3rd-order , 2-channel D/A Converter |
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