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參數(shù)資料
| 型號： | SM840004-11KA TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SYNTHESIZER LN 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | High Bandwidth Product Overview |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | RotaryWave™ |
| 類型： | 時鐘/頻率合成器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng) |
| 輸入： | 晶體 |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 125MHz |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
MCP795W1X/MCP795W2X
DS22280C-page 6
Preliminary
2011-2012 Microchip Technology Inc.
2.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 2-1.
FIGURE 2-1:
DEVICE PINOUTS
2.1
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go in Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes into the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
2.2
Serial Output (SO)
The SO pin is used to transfer data out of the
MCP795WXX. During a read cycle, data is shifted out
on this pin after the falling edge of the serial clock.
2.3
Watchdog Output (WDO)
This pin is a hardware open drain from the internal
watchdog circuit. This pin requires an external pull-up
to VCC. When a watchdog overflow occurs the on-
board N-Channel will pulse this pin low. The pulse
duration is user selectable (Address 0x0A:4). This pin
has a maximum sink current of 10mA.
2.4
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
2.5
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the MCP795WXX. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
2.6
Interrupt Output (IRQ)
The IRQ pin is shared with the on-board event detect
and the alarms. This pin requires an external pull-up to
VCC or VBAT. The on-board N-Channel will pull the pin
low during an event detection or an alarm. The pin
remains low until such time that the interrupt flag in the
register is cleared by software. This pin has a
maximum sink current of 10mA.
2.7
X1, X2
The X1 and X2 pins connect to the on-board oscillator
block. X1 is the input to the module and X2 is the out-
put of the module. The device can be run from an
external CMOS signal by feeding into the X1 pin. If
driving X1 the X2 pin should be a No Connect.
2.8
VBAT
The VBAT pin is a secondary supply input to maintain
the Clock and SRAM contents when VCC is removed.
2.9
CLKOUT
The CLKOUT is a push-pull output that can be used to
generate a squarewave. Please refer to Section 9.1.2,
Clockout Function for more details.
2.10
EVHS and EVLS
The EVHS and EVLS are inputs for the High and Low
Speed Event Detection circuit.
TABLE 2-1:
PIN DESCRIPTIONS
X1
X2
VBAT
WDO
Vcc
CLKOUT
EVHS
EVLS
1
2
3
4
14
13
12
11
MCP
7
95
W
X
SOIC/TSSOP
IRQ
CS
VSS
SCK
SI
SO
5
6
7
10
9
8
Pin Name
Pin Function
VSS
Ground
X1
Xtal Input, External Oscillator Input
X2
Xtal Output
VBAT
Battery Backup Input (3V Typ)
VCC
+1.8V to +3.6V Power Supply
SI
Serial Input
WDO
Watchdog Output
SCK
Serial Clock
CLKOUT
Clock Out
CS
Chip Select
IRQ
Interrupt Output
EVHS
High-Speed Event Detect Input
EVLS
Low-Speed Event Detect Input
SO
Serial Output
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