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參數(shù)資料
| 型號(hào)： | SM89516P |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8 - Bit Micro-controller with 64KB flash & 1KB RAM embedded |
| 中文描述： | 8 -位微控制器，64KB閃存 |
| 文件頁數(shù)： | 8/19頁 |
| 文件大?。?/td> | 436K |
| 代理商： | SM89516P |
May 2001
Specifications subject to change without notice,contact your sales representatives for the most recent information.
8/19 Ver 1.3 PID 89516 05/01
SyncMOS Technologies Inc. SM89516
Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)
WDTE: Watch Dog Timer enable bit
CLEAR: Watch Dog Timer reset bit
PS2 ~ PS0: clock source divider selection bit
PS [2:0]
Divider (OSC in)
Time Period (ms) @40MHz
000
8
13.1
001
16
26.21
010
32
52.42
011
64
104.8
100
128
209.71
101
256
419.43
110
512
838.86
111
1024
1677.72
System Control Register (SCONF, $BF)
The bit 7(WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated
by WDT overflow. User should check WDR bit whenever un-predicted reset happened.
Reduce EMI Function
The SM89516 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This
function will inhibit the clock signal in Fosc/6Hz output to the ALE pin. This function is available when there is
no external program memory or no external data RAM in the system.
WDTE
Unused
CLEAR
Unused
Unused
PS2
PS1
PS0
0
*
0
*
*
0
0
0
WDR
Unused
Unused
Unused
Unused
Unused
OME
ALEI
0
*
*
*
*
*
1
0
Reset
value
MSB
LSB
Reset
value
MSB
LSB
WDR: Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1
OME: 768 bytes on-chip RAM enable bit
ALEI: ALE output inhibit bit, to reduce EMI
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| SM89516Q | 制造商:SYNCMOS 制造商全稱:SYNCMOS 功能描述:8 - Bit Micro-controller with 64KB flash & 1KB RAM embedded |
| SM8951A | 制造商:SYNCMOS 制造商全稱:SYNCMOS 功能描述:8-Bits Micro-controller With 4/8KB flash embedded |
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| SM8951AC40 | 制造商:SYNCMOS 制造商全稱:SYNCMOS 功能描述:8-Bits Micro-controller With 4/8KB flash embedded |
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