
SyncMOS Technologies Inc. SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded
Addressing Mode
Notes on instruction set and address modes:
Rn
Register R7-R0 of the currently selected register bank.
direct
8-bits internal data location’s address. This could be internal DATA RAM location (0-127) or a
SFR [i.e., I/O port, control register, status register, etc. (128-255)]
@Ri
8-bits RAM location addressed indirectly through register R1 or R0 of the actual register bank
#data
8-bits constant included in the instruction
#data16
16-bits constant included in the instruction
addr11
11-bits destination address. Used by ACALL and AJMP. The branch can be anywhere within the
same 2 Kbytes page of program memory as the first byte of the following instruction.
rel
Signed (2’s complement) 8-bits offset byte. Used by SJMP and all conditional jumps. Range is
-128 to +127 bytes relative to first byte of the following instruction.
bit
Direct addressed bit in internal data RAM or SFR
Table 3: A Summary of the instruction set
Mnemonic
OPERATION
Arithmetic Instructions
ADD
A,Rn
A = A + Rn
ADD
A,direct
A = A + direct
ADD
A,@Ri
A = A + <@Ri>
ADD
A,#data
A = A + #data
ADDC
A,Rn
A = A + Rn + C
ADDC
A,direct
A = A + direct + C
Specifications subject to change without notice contact your sales representatives for the most recent information.
SM89S16R1 V1.0 JANUARY 2005
17
BYTE
CYCLE
1
2
1
2
1
2
1
1
1
1
1
1
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
INC
INC
INC
DEC
DEC
DEC
DEC
INC
MUL
DIV
A,@Ri
A,#data
A,Rn
A,direct
A,@Ri
A,#data
A
Rn
direct
@Ri
A
Rn
direct
@Ri
DPTR
AB
AB
A = A + @Ri + C
A = A + #data + C
A = A
-
Rn
-
C
A = A
-
direct
-
C
A = A
-
<@Ri>
-
C
A = A
-
#data
-
C
A = A + 1
Rn = Rn + 1
direct = direct + 1
<@Ri> = <@Ri> + 1
A = A
-
1
Rn = Rn
-
1
direct = direct
-
1
<@Ri> = <@Ri>
-
1
DPTR = DPTR
-
1
B:A = A
×
B
A = INT (A/B)
B = MOD (A/B)
Decimal adjust ACC
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
DA
Logical Instructions
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
A
1
1
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A .AND. Rn
A .AND. direct
A .AND. <@Ri>
A .AND. #data
direct .AND. A
direct .AND. #data
A .OR. Rn
A .OR. direct
A .OR. <@Ri>
A .OR. #data
direct .OR. A
direct .OR. #data
A .XOR. Rn
A .XOR. direct
A .XOR. <@Ri>
A .XOR. #data
direct .XOR. A
direct .XOR. #data
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2