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參數(shù)資料
| 型號： | SM8R-67025L-45/883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | SRAM |
| 英文描述： | 8K X 16 DUAL-PORT SRAM, 45 ns, CPGA84 |
| 封裝： | PGA-84 |
| 文件頁數(shù)： | 6/23頁 |
| 文件大小： | 257K |
| 代理商： | SM8R-67025L-45/883 |
M 67025
MATRA MHS
Rev. D (29/09/95)
14
Timing Waveform of Read Cycle n
° 1, Either Side (1, 2, 4)
Timing Waveform of Read Cycle n
° 2, Either Side (1, 3, 5)
Timing Waveform of Read Cycle n
° 3, Either Side (1, 3, 4, 5)
Notes :
1. R/W is high for read cycles.
2. Device is continuously enabled, CS = VIL, UB or LB = VIL. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CS transition low.
4. OE = VIL.
5. To access RAM, CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CS = VIH, SEM = VIL. Refer to table 1.
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