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參數(shù)資料
| 型號： | SMJ4164-15FGE |
| 英文描述： | x1 Page Mode DRAM |
| 中文描述： | x1頁面模式的DRAM |
| 文件頁數(shù)： | 7/25頁 |
| 文件大小： | 437K |
| 代理商： | SMJ4164-15FGE |
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
’416100-60
’416100P-60
’416100-70
’416100P-70
’416100-80
’416100P-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
VOH
VOL
High-level output voltage
IOH = – 5 mA
IOL = 4.2 mA
VI = 0 V to 6.5 V
All other pins = 0 V to VCC
VO = 0 V to VCC, CAS high
2.4
2.4
2.4
V
Low-level output voltage
0.4
0.4
0.4
V
II
Input current (leakage)
±
10
±
10
±
10
μ
A
IO
Output current (leakage)
±
10
±
10
±
10
μ
A
ICC1
Read- or write-cycle
current
(see Notes 3 and 5)
VCC = 5.5 V,
Minimum cycle
80
70
60
mA
ICC2
Standby current
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V (TTL)
After 1 memory cycle,
RAS and CAS high,
VIH = VCC – 0.2 V (CMOS)
2
2
2
mA
’416100
1
1
1
mA
’416100P
500
500
500
μ
A
ICC3
Average refresh current
(RAS-only or CBR)
(see Notes 3 and 5)
RAS cycling,
RAS low after CAS low (CBR)
CAS high (RAS-only);
80
70
60
mA
ICC4
Average page current
(see Notes 4 and 5)
RAS low,
CAS cycling
70
60
50
mA
ICC6
Self-refresh current
(’416100P only)
CAS and RAS < 0.2 V,
Measured after tRASS min
500
500
500
μ
A
ICC7
Standby current,
output enable
(see Note 5)
RAS = VIH,
Data out = enabled
CAS = VIL,
5
5
5
mA
ICC10
Extended-refresh battery
backup (’416100P only)
tRC = 62.5
μ
s,
VCC – 0.2 V
≤
VIH
≤
6.5 V,
0 V
≤
VIL
≤
0.2 V, W and OE = VIH,
Address and data stable
tRAS
≤
1
μ
s,
500
500
500
μ
A
Minimum cycle, VCC = 5.5 V
NOTES:
3. Measured with a maximum of one address change while RAS = VIL
4. Measured with a maximum of one address change while CAS = VIH
5. Measured with no load connected
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