參數(shù)資料
型號(hào): SN54ABT5402AJT
廠商: Texas Instruments, Inc.
英文描述: 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS
中文描述: 12位線/記憶體驅(qū)動(dòng)器,三態(tài)輸出
文件頁(yè)數(shù): 2/6頁(yè)
文件大小: 105K
代理商: SN54ABT5402AJT
SN54ABT5402A, SN74ABT5402A
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS660B – FEBRUARY 1996 – REVISED MAY 1997
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
28
D1
27
D2
26
D3
25
D4
24
D5
Y1
1
Y2
2
Y3
3
Y4
4
Y5
5
Y6
6
Y7
8
Y8
9
23
D6
22
D7
20
D8
15
14
OE1
OE2
EN
&
Y9
10
Y10
11
19
D9
18
D10
1
17
D11
Y11
12
16
D12
Y12
13
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the DW and JT packages.
logic diagram (positive logic)
Y1
To Eleven Other Channels
OE1
OE2
D1
14
15
28
1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
Input voltage range, V
I
(see Note 1)
Voltage range applied to any output in the high or power-off state, V
O
Current into any output in the low state, I
O
Input clamp current, I
IK
(V
I
< 0)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
θ
JA
(see Note 2): DW package
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
–0.5 V to 7 V
–0.5 V to 7 V
–0.5 V to 5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . .
30 mA
–18 mA
–50 mA
78
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65
°
C to 150
°
C
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