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參數(shù)資料
| 型號： | SN54AC564FK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS |
| 中文描述： | 八路D型沿觸發(fā)器與觸發(fā)器3態(tài)輸出 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 121K |
| 代理商： | SN54AC564FK |
SN54AC564, SN74AC564
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS551A – NOVEMBER 1995 – REVISED MAY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3-State Inverting Outputs Drive Bus Lines
Directly
Full Parallel Access for Loading
Flow-Through Architecture to Optimize
PCB Layout
EPIC
(Enhanced-Performance Implanted
CMOS) 1-
μ
m Process
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
description
The ’AC564 are octal D-type edge-triggered
flip-flops that feature inverting 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
On the positive transition of the clock (CLK) input,
the Q outputs are set to the inverse logic levels set
up at the data (D) inputs.
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54AC564 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C. The
SN74AC564 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLK
↑
↑
H or L
OUTPUT
Q
OE
D
L
H
L
L
L
H
L
X
Q0
Z
H
X
X
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
SN54AC564 . . . J OR W PACKAGE
SN74AC564 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2
1
O
8
7
1
8
G
C
V
C
SN54ACT564 . . . FK PACKAGE
(TOP VIEW)
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
parameters.
Copyright
1996, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54AC564J | OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS |
| SN54AC564W | OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS |
| SN74AC564DWR | OCTAL D-TYPE EDGE-TRIGGERDE FLIP-FLOPS WITH 3-STATE OUTPUTS |
| SN74AC564DWRE4 | OCTAL D-TYPE EDGE-TRIGGERDE FLIP-FLOPS WITH 3-STATE OUTPUTS |
| SN74AC564NSR | OCTAL D-TYPE EDGE-TRIGGERDE FLIP-FLOPS WITH 3-STATE OUTPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54AC564J | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS |
| SN54AC564W | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS |
| SN54AC573 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS |
| SN54AC573_06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS |
| SN54AC573FK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS |
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