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參數(shù)資料
| 型號： | SN54LS113J |
| 廠商： | Motorola, Inc. |
| 英文描述： | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| 中文描述： | 雙JK負邊沿觸發(fā)器 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 140K |
| 代理商： | SN54LS113J |
5-189
FAST AND LS TTL DATA
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54/74LS113A offers individual J, K, set, and clock inputs. These
monolithic dual flip-flops are designed so that when the clock goes HIGH, the
inputs are enabled and data will be accepted. The logic level of the J and K
inputs may be allowed to change when the clock pulse is HIGH and the
bistable will perform according to the truth table as long as minimum setup
times are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
LOGIC DIAGRAM
(Each Flip-Flop)
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS
OUTPUTS
SD
L
H
H
H
H
J
K
Q
Q
Set
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
X
h
l
h
l
X
h
h
l
l
H
q
L
H
q
L
q
H
L
q
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) =
one set-up time prior to the HIGH to LOW clock transition.
SN54/74LS113A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC SYMBOL
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14
1
14
1
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
14
1
D SUFFIX
SOIC
CASE 751A-02
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| SN54LS114A | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| SN54LS114J | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
| SN74LS114D | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
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