參數(shù)資料
型號: SN54LS168
廠商: Motorola, Inc.
元件分類: 通用總線功能
英文描述: BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS
中文描述: BCD碼十年/模16二進(jìn)制同步的雙向計(jì)數(shù)器
文件頁數(shù): 4/8頁
文件大?。?/td> 272K
代理商: SN54LS168
5-305
FAST AND LS TTL DATA
SN54/74LS168
SN54/74LS169
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
74
0.8
VIK
Input Clamp Diode Voltage
–0.65
–1.5
V
VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54
2.5
3.5
V
or VIL per Truth Table
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
per Truth Table
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
IIH
Input HIGH Current
Other Inputs
CET Input
20
40
μ
A
VCC = MAX, VIN = 2.7 V
Other Input
CET Input
0.1
0.2
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
Other Input
CET Input
–0.4
–0.8
mA
VCC = MAX, VIN = 0.4 V
IOS
ICC
Note 1: Not more than one output should be shorted at one time, nor for more than 1 second.
Short Circuit Current (Note 1)
–20
–100
mA
VCC = MAX
VCC = MAX
Power Supply Current
34
mA
FUNCTIONAL DESCRIPTION
The SN54/74LS168 and SN54/74LS169 use edge-
triggered D-type flip-flops that have no constraints on
changing the control or data input signals in either state of the
Clock. The only requirement is that the various inputs attain
the desired state at least a set-up time before the rising edge of
the clock and remain valid for the recommended hold time
thereafter.
The parallel load operation takes precedence over the other
operations, as indicated in the Mode Select Table. When PE is
LOW, the data on the P0–P3 inputs enters the flip-flops on the
next rising edge of the Clock. In order for counting to occur,
both CEP and CET must be LOW and PE must be HIGH. The
U/D input then determines the direction of counting.
The Terminal Count (TC) output is normally HIGH and goes
LOW, provided that CET is LOW, when a counter reaches zero
in the COUNT DOWN mode or reaches 15 (9 for the
SN54/74LS168) in the COUNT UP mode. The TC output state
is not a function of the Count Enable Parallel (CEP) input level.
The TC output of the SN54/74LS168 decade counter can also
be LOW in the illegal states 11, 13 and 15, which can occur
when power is turned on or via parallel loading. If illegal state
occurs, the SN54/74LS168 will return to the legitimate
sequence within two counts. Since the TC signal is derived by
decoding the flip-flop states, there exists the possibility of
decoding spikes on TC. For this reason the use of TC as a
clock signal is not recommended.
MODE SELECT TABLE
PE
CEP
CET
U/D
Action on Rising Clock Edge
L
H
H
X
L
L
X
L
L
X
H
L
Load (Pn
o
Qn)
Count Up (increment)
Count Down (decrement)
H
H
H
X
X
H
X
X
No Change (Hold)
No Change (Hold)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
相關(guān)PDF資料
PDF描述
SN54LS168J BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS
SN54LS191J PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS
SN74LS190D PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS
SN74LS190N axial lead glass packaged PIN diodes
SN74LS191D Silicon Bipolar Darlington Amplifier
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