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參數(shù)資料
| 型號(hào)： | SN54LS174 |
| 廠商： | Motorola, Inc. |
| 英文描述： | HEX D FLIP-FLOP |
| 中文描述： | 六角D觸發(fā)器 |
| 文件頁數(shù)： | 3/3頁 |
| 文件大?。?/td> | 75K |
| 代理商： | SN54LS174 |
5-3
FAST AND LS TTL DATA
SN54/74LS174
AC CHARACTERISTICS
(TA = 25
°
C)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
fMAX
tPHL
tPLH
tPHL
Maximum Input Clock Frequency
30
40
MHz
CL = 15 pF
Propagation Delay, MR to Output
23
35
ns
VCC = 5.0 V
Propagation Delay, Clock to Output
20
21
30
30
ns
AC SETUP REQUIREMENTS
(TA = 25
°
C)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
tW
ts
th
Clock or MR Pulse Width
20
ns
VCC = 5.0 V
Data Setup Time
20
ns
Data Hold Time
5.0
ns
trec
Recovery Time
25
ns
AC WAVEFORMS
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
*The shaded areas indicate when the input is permitted to
*
change for predictable output performance.
1.3 V
1.3 V
1.3 V
tPLH
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1/fmax
tw
ts(H)
th(H)
ts(L)
th(L)
CP
tPHL
tW
tPHL
CP
trec
Q
MR
D
Q
*
1.3 V
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW to HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW to
HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and transfer
HIGH Data to the Q outputs.
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