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參數(shù)資料
| 型號： | SN54LS197J |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-STAGE PRESETTABLE RIPPLE COUNTERS |
| 中文描述： | LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 227K |
| 代理商： | SN54LS197J |
5-376
FAST AND LS TTL DATA
SN54/74LS196
SN54/74LS197
AC CHARACTERISTICS
(TA = 25
°
C)
Symbol
Parameter
Limits
Unit
Test Conditions
LS196
LS197
Min
Typ
Max
Min
Typ
Max
fMAX
tPLH
tPHL
Maximum Clock Frequency
30
40
30
40
MHz
CL = 15 pF
CP0 Input to
Q0 Output
8.0
13
15
20
8.0
14
15
21
ns
VCC = 5.0 V
tPLH
tPHL
CP1 Input to
Q1 Output
16
22
24
33
12
23
19
35
ns
tPLH
tPHL
CP1 Input to
Q2 Output
38
41
57
62
34
42
51
63
ns
tPLH
tPHL
CP1 Input to
Q3 Output
12
30
18
45
55
63
78
95
ns
tPLH
tPHL
Data to Output
20
29
30
44
18
29
27
44
ns
tPLH
tPHL
PL Input to
Any Output
27
30
41
45
26
30
39
45
ns
tPHL
MR Input to Any Output
34
51
34
51
ns
AC SETUP REQUIREMENTS
(TA = 25
°
C)
Symbol
Parameter
Limits
Unit
Test Conditions
LS196
LS197
Min
Typ
Max
Min
Typ
Max
tW
tW
tW
tW
ts
ts
th
CP0 Pulse Width
CP1 Pulse Width
PL Pulse Width
20
20
ns
VCC = 5.0 V
30
30
ns
20
20
ns
MR Pulse Width
15
15
ns
Data Input Setup Time — HIGH
10
10
ns
Data Input Setup Time — LOW
15
15
ns
Data Hold Time — HIGH
10
10
ns
th
trec
Data Hold Time — LOW
10
10
ns
Recovery Time
30
30
ns
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from HIGH to LOW in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from HIGH to LOW that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from HIGH to
LOW and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from HIGH to LOW in order to recognize and transfer
LOW Data to the Q outputs.
相關PDF資料 |
PDF描述 |
|---|---|
| SN74LS196D | 4-STAGE PRESETTABLE RIPPLE COUNTERS |
| SN74LS196N | Demonstration Circuit Board for AMMP-6530 (Mixer) |
| SN74LS197D | Demonstration Circuit Board |
| SN74LS197N | Demonstration circuit board for MGA-81563 and MGA-82563 |
| SN54LS249 | BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS |
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