參數(shù)資料
型號: SN54LS279
廠商: Motorola, Inc.
英文描述: 8-Bit Addressable Latch; Package: SOEIAJ-16; No of Pins: 16; Container: Rail; Qty per Container: 50
中文描述: 四設置復位鎖存
文件頁數(shù): 2/4頁
文件大?。?/td> 130K
代理商: SN54LS279
5-453
FAST AND LS TTL DATA
SN54/74LS279
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
74
0.8
VIK
Input Clamp Diode Voltage
–0.65
–1.5
V
VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54
2.5
3.5
V
or VIL per Truth Table
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
per Truth Table
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
IIH
Input HIGH Current
20
μ
A
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
0.1
mA
IIL
IOS
ICC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
Input LOW Current
–0.4
mA
Short Circuit Current (Note 1)
–20
–100
mA
Power Supply Current
7.0
mA
AC CHARACTERISTICS
(TA = 25
°
C)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
tPLH
tPHL
Propagation Delay, S to Output
22
*
21*
ns
VCC = 5.0 V
CL = 15 pF
tPHL
* Add 0.6 ns to spec limit for each 1.0 ns input rise time less than 15 ns.
Propagation Delay, R to Output
27
ns
相關PDF資料
PDF描述
SN74LS279D QUAD SET-RESET LATCH
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