參數(shù)資料
型號： SN54LS293J
廠商： MOTOROLA INC
元件分類： 通用總線功能
英文描述： DECADE COUNTER; 4-BIT BINARY COUNTER
中文描述： LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, CDIP14
封裝： CERAMIC, DIP-14
文件頁數(shù)： 5/7頁
文件大小： 205K
代理商： SN54LS293J
5-470
FAST AND LS TTL DATA
SN54/74LS290 SN54/74LS293
AC CHARACTERISTICS
(TA = 25
°
C, VCC = 5.0 V, CL = 15 pF)
Symbol
Parameter
Limits
Unit
LS290
LS293
Min
Typ
Max
Min
Typ
Max
fMAX
fMAX
tPLH
tPHL
CP0 Input Clock Frequency
CP1 Input Clock Frequency
Propagation Delay,
CP0 Input to Q0 Output
32
32
MHz
16
16
MHz
10
12
16
18
10
12
16
18
ns
tPLH
tPHL
CP0 Input to Q3 Output
32
34
48
50
46
46
70
70
ns
tPLH
tPHL
CP1 Input to Q1 Output
10
14
16
21
10
14
16
21
ns
tPLH
tPHL
CP1 Input to Q2 Output
21
23
32
35
21
23
32
35
ns
tPLH
tPHL
CP1 Input to Q3 Output
21
23
32
35
34
34
51
51
ns
tPHL
tPHL
tPHL
MS Input to Q0 and Q3 Outputs
MS Input to Q1 and Q2 Outputs
MR Input to Any Output
20
30
ns
26
40
ns
26
40
26
40
ns
AC SETUP REQUIREMENTS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
LS290
LS293
Min
Max
Min
Max
tW
tW
tW
tW
trec
CP0 Pulse Width
CP1 Pulse Width
MS Pulse Width
15
15
ns
30
30
ns
15
ns
MR Pulse Width
15
15
ns
Recovery Time MR to CP
25
25
ns
RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition form HIGH-to-LOW in order to
recognize and transfer HIGH data to the Q outputs.
Figure 1
Figure 2
Figure 3
*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.
AC WAVEFORMS
相關(guān)PDF資料
PDF描述
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