參數(shù)資料
型號: SN54LS398
廠商: Motorola, Inc.
英文描述: Dual 1-of-4 Decoder/Demultiplexer; Package: SOIC 16 LEAD; No of Pins: 16; Container: Tape and Reel; Qty per Container: 2500
中文描述: 四2端口寄存器
文件頁數(shù): 4/6頁
文件大?。?/td> 209K
代理商: SN54LS398
5-560
FAST AND LS TTL DATA
SN54/74LS398
SN54/74LS399
AC SETUP REQUIREMENTS
(TA = 25
°
C)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
tW
ts
ts
th
Clock Pulse Width
20
ns
VCC = 5.0 V
Data Setup Time
25
ns
Select Setup Time
45
ns
Hold Time, Any Input
0
ns
DEFINITIONS OF TERMS
SETUP TIME(ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME(th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative Hold Time indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
AC WAVEFORMS
Figure 1
Figure 2
Figure 3
*The shaded areas indicate when the input is permitted to change for predictable output performance.
相關(guān)PDF資料
PDF描述
SN54LS398J Dual 1-of-4 Decoder/Demultiplexer; Package: SOIC 16 LEAD; No of Pins: 16; Container: Tape and Reel; Qty per Container: 2500
SN54LS399J QUAD 2-PORT REGISTER
SN74LS398D QUAD 2-PORT REGISTER
SN74LS398N QUAD 2-PORT REGISTER
SN74LS399D QUAD 2-PORT REGISTER
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