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參數資料
| 型號： | SN54LVTH574J |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Dual D-Type Flip-Flop with Set and Reset; Package: SOIC 14 LEAD; No of Pins: 14; Container: Rail; Qty per Container: 55 |
| 中文描述： | 的3.3V ABT生根粉八路邊沿觸發(fā)的D型倒裝3觸發(fā)器態(tài)輸出 |
| 文件頁數： | 5/7頁 |
| 文件大?。?/td> | 94K |
| 代理商： | SN54LVTH574J |
SN54LVTH574, SN74LVTH574
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS688D – MAY 1997 – REVISED APRIL 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH574
VCC = 3.3 V
±
0.3 V
SN74LVTH574
VCC = 3.3 V
±
0.3 V
VCC = 2.7 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fclock
tw
tsu
th
Clock frequency
150
150
150
150
MHz
Pulse duration, CLK high or low
Setup time, data before CLK
↑
Hold time, data after CLK
↑
3.3
3.3
3.3
3.3
ns
2
2.4
2
2.4
ns
0.9
0.9
0.3
0
ns
switching characteristics over recommended free-air temperature, C
L
= 50 pF (unless otherwise
noted) (see Figure 1)
SN54LVTH574
VCC = 3.3 V
±
0.3 V
SN74LVTH574
VCC = 3.3 V
±
0.3 V
TYP
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.7 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
150
150
150
150
MHz
CLK
Q
1.7
4.9
5.9
1.8
3
4.5
5.3
ns
1.7
4.9
5.5
1.8
3
4.5
5.3
OE
Q
1.4
5.1
6.5
1.5
3.2
4.8
5.9
ns
1.4
5.1
6.1
1.5
3.5
4.8
5.9
OE
Q
1
5.9
6.4
2
3.5
4.8
5.1
ns
0.8
4.8
5.3
2
3.2
4.4
4.4
All typical values are at VCC = 3.3 V, TA = 25
°
C.
相關PDF資料 |
PDF描述 |
|---|---|
| SN54LVTH574W | Dual D-Type Flip-Flop with Set and Reset; Package: SOIC 14 LEAD; No of Pins: 14; Container: Rail; Qty per Container: 55 |
| SN54LVTT240 | 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| SN54LVTT240FK | 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| SN54LVTT240J | 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| SN54LVTT240W | 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
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