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| 型號： | SN74ABT3614PQ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 64 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING |
| 中文描述： | 64】36】2時鐘雙向第一的，在總線匹配和字節(jié)交換先出存儲器 |
| 文件頁數(shù)： | 8/41頁 |
| 文件大小： | 636K |
| 代理商： | SN74ABT3614PQ |
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SN74ABT3614
64
×
36
×
2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS126H – JUNE 1992 – REVISED APRIL 2000
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FIFO writer/read operation (continued)
Table 3. Port-B Enable Function Table
CSB
W/RB
ENB
SIZ1, SIZ0
CLKB
B0–B35 OUTPUTS
PORT FUNCTION
H
X
X
X
X
In high-impedance state
None
L
H
L
X
X
↑
↑
X
↑
X
↑
In high-impedance state
None
L
H
H
One, both low
In high-impedance state
FIFO2 write
L
H
H
Both high
In high-impedance state
Mail2 write
L
L
L
One, both low
Active, FIFO1 output register
None
L
L
H
One, both low
Active, FIFO1 output register
FIFO1 read
L
L
L
Both high
Active, mail1 register
None
L
L
H
Both high
Active, mail1 register
Mail1 read (set MBF1 high)
synchronized FIFO flags
Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability
by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously
to one another. EFA, AEA, FFA, and AFA are synchronized to CLKA. EFB, AEB, FFB, and AFB are synchronized
to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2.
Table 4. FIFO1 Flag Operation
NUMBER OF 36-BIT
WORDS IN FIFO1
SYNCHRONIZED
TO CLKB
SYNCHRONIZED
TO CLKA
EFB
L
AEB
L
AFA
H
FFA
H
0
1 to X
H
L
H
H
(X + 1) to [64 – (X + 1)]
H
H
H
H
(64 – X) to 63
H
H
L
H
64
H
H
L
L
X is the value in the AE flag and AF flag offset register.
Table 5. FIFO2 Flag Operation
NUMBER OF 36-BIT
WORDS IN FIFO2
SYNCHRONIZED
TO CLKA
SYNCHRONIZED
TO CLKB
EFA
L
AEA
L
AFB
H
FFB
H
0
1 to X
H
L
H
H
(X + 1) to [64 – (X + 1)]
H
H
H
H
(64 – X) to 63
H
H
L
H
64
H
H
L
L
X is the value in the AE flag and AF flag offset register.
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