參數(shù)資料
型號: SN74ABT373PWRG4
廠商: Texas Instruments
文件頁數(shù): 18/21頁
文件大?。?/td> 0K
描述: IC OCTAL TRANSPAR D 3ST 20-TSSOP
標準包裝: 2,000
系列: 74ABT
邏輯類型: D 型透明鎖存器
電路: 8:8
輸出類型: 三態(tài)
電源電壓: 4.5 V ~ 5.5 V
獨立電路: 1
延遲時間 - 傳輸: 4.6ns
輸出電流高,低: 32mA,64mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-TSSOP
包裝: 帶卷 (TR)
SN54ABT373, SN74ABT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS155D – JANUARY 1991 – REVISED MAY 1997
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500
500
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V
3 V
0 V
3 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPLH
VOH
VOL
1.5 V
3 V
0 V
1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈ 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 , tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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