參數(shù)資料
型號(hào): SN74ALS568ADW
廠商: Texas Instruments, Inc.
元件分類: 通用總線功能
英文描述: SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS
中文描述: 同步4位向上/向下十年和二進(jìn)制計(jì)數(shù)器具有三態(tài)輸出
文件頁數(shù): 1/20頁
文件大?。?/td> 610K
代理商: SN74ALS568ADW
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
Copyright
1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3-State Q Outputs Drive Bus Lines Directly
Counter Operation Independent of 3-State
Output
Fully Synchronous Clear, Count, and Load
Asynchronous Clear Is Also Provided
Fully Cascadable
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
description
The
ALS569A binary counters are programmable,
count up or down, and offer both synchronous and
asynchronous clearing. All synchronous functions
are executed on the positive-going edge of the
clock (CLK) input.
SN74ALS568A
decade
counter
and
The clear function is initiated by applying a low
level to either asynchronous clear (ACLR) or
synchronous clear (SCLR). Asynchronous (direct)
clearing overrides all other functions of the device,
while synchronous clearing overrides only the
other synchronous functions. Data is loaded from
the A, B, C, and D inputs by holding load (LOAD)
low during a positive-going clock transition. The
counting function is enabled only when enable P
(ENP) and enable T (ENT) are low and ACLR,
SCLR, and LOAD are high. The up/down (U/D)
input controls the direction of the count. These
counters count up when U/D is high and count
down when U/D is low.
A high level at the output-enable (OE) input forces the Q outputs into the high-impedance state, and a low level
enables those outputs. Counting is independent of OE. ENT is fed forward to enable the ripple-carry output
(RCO) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum
(9 or 15) when counting up. The clocked carry output (CCO) produces a low-level pulse for a duration equal to
that of the low level of the clock when RCO is low and the counter is enabled (both ENP and ENT are low);
otherwise, CCO is high. CCO does not have the glitches commonly associated with a ripple-carry output.
Cascading is normally accomplished by connecting RCO or CCO of the first counter to ENT of the next counter.
However, for very high-speed counting, RCO should be used for cascading since CCO does not become active
until the clock returns to the low level.
The SN54ALS569A is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74ALS568A and SN74ALS569A are characterized for operation from 0
°
C to 70
°
C.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
U/D
CLK
A
B
C
D
ENP
ACLR
SCLR
GND
V
CC
RCO
CCO
OE
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
SN54ALS569A . . . J PACKAGE
SN74ALS568A, SN74ALS569A . . . DW OR N PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
CCO
OE
Q
A
Q
B
Q
C
B
C
D
ENP
ACLR
SN54ALS569A . . . FK PACKAGE
(TOP VIEW)
A
C
U
E
Q
R
S
G
L
V
C
D
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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SN74ALS569ADWG4 功能描述:計(jì)數(shù)器 IC Synch 4B Up Down Binary Counters RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel
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