參數(shù)資料
型號(hào)： SN74ALVC16952
廠商： Texas Instruments, Inc.
英文描述： 16-Bit Registered Transceivers(16位記錄接收傳送器(三態(tài)輸出))
中文描述： 16位注冊(cè)收發(fā)器（16位記錄接收傳送器（三態(tài)輸出））
文件頁(yè)數(shù)： 1/6頁(yè)
文件大?。?/td> 128K
代理商： SN74ALVC16952
SN74ALVC16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS277 – JANUARY 1993 – REVISED MARCH 1994
Copyright
1994, Texas Instruments Incorporated
9–1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
Designed to Facilitate Incident-Wave
Switching for Line Impedances of 50
or Greater
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Bus-Hold On Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit registered transceiver is designed for
2.7-V to 3.6-V V
CC
operation.
The SN74ALVC16952 contains two sets of D-type
flip-flops for temporary storage of data flowing in
either direction. It can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the
A or B bus is stored in the registers on the
low-to-high transition of the clock (CLKAB or
CLKBA) input provided that the clock-enable
(CEAB or CEBA) input is low. Taking the
output-enable (OEAB or OEBA) input low
accesses the data on either port.
The SN74ALVC16952 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same
printed-circuit-board area.
The SN74ALVC16952 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
INPUTS
OUTPUT
B
CLKENAB
H
CLKAB
OEAB
L
A
X
X
B0
B0
L
X
L
↑
↑
X
L
X
L
L
L
L
L
H
H
X
H
X
Z
A-to-B data flow is shown; B-to-A data flow is similar
but uses CLKENBA, CLKBA, and OEBA.
Level of B before the indicated steady-state input
conditions were established.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEAB
1CLKAB
1CEAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2CEAB
2CLKAB
2OEAB
1OEBA
1CLKBA
1CEBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CEBA
2CLKBA
2OEBA
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
P
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