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參數(shù)資料
| 型號(hào)： | SN74AVCH4T245PWT |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 2/24頁 |
| 文件大小： | 0K |
| 描述： | IC BUS TRANSCVR 4BIT 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 74AVCH |
| 邏輯功能： | 變換器，雙向，3 態(tài) |
| 位數(shù)： | 2 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 數(shù)據(jù)速率： | 380Mbps |
| 通道數(shù)： | 1 |
| 輸出/通道數(shù)目： | 2 |
| 差分 - 輸入:輸出： | 無/無 |
| 傳輸延遲（最大）： | 2.9ns |
| 電源電壓： | 1.2 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 296-29002-6 |
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VOH
VOL
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
2
× VCCO
Open
GND
RL
tPLH
tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
× VCCO
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VCCA/2
VCCI/2
VCCI
0 V
VCCO/2
VOH
VOL
0 V
VCCO/2
VOL + VTP
VCCO/2
VOH VTP
0 V
VCCI
0 V
VCCI/2
tw
Input
VCCA
VCCO
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2
× VCCO
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 , dv/dt ≥ 1 V/ns,
dv/dt
≥1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
1.2 V
1.5 V
± 0.1 V
1.8 V
± 0.15 V
2.5 V
± 0.2 V
3.3 V
± 0.3 V
2 k
2 k
2 k
2 k
2 k
VCCO
RL
0.1 V
0.15 V
0.3 V
VTP
CL
15 pF
4-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES577D – JUNE 2004 – REVISED JUNE 2007
Figure 1. Load Circuit and Voltage Waveforms
10
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