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參數(shù)資料
| 型號： | SN74LS166N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 1.7 - 2.7GHz 2 Watt High Linearity Amplifier |
| 中文描述： | LS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| 封裝： | 648-08 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 106K |
| 代理商： | SN74LS166N |
5-1
FAST AND LS TTL DATA
8-BIT SHIFT REGISTERS
The SN54L/74LS166 is an 8-Bit Shift Register. Designed with all inputs
buffered, the drive requirements are lowered to one 54/74LS standard load.
By utilizing input clamping diodes, switching transients are minimized and
system design simplified.
The LS166 is a parallel-in or serial-in, serial-out shift register and has a
complexity of 77 equivalent gates with gated clock inputs and an overriding
clear input. The shift/load input establishes the parallel-in or serial-in mode.
When high, this input enables the serial data input and couples the eight
flip-flops for serial shifting with each clock pulse. Synchronous loading occurs
on the next clock pulse when this is low and the parallel data inputs are
enabled. Serial data flow is inhibited during parallel loading. Clocking is done
on the low-to-high level edge of the clock pulse via a two input positive NOR
gate, which permits one input to be used as a clock enable or clock inhibit
function. Clocking is inhibited when either of the clock inputs are held high,
holding either input low enables the other clock input. This will allow the
system clock to be free running and the register stopped on command with
the other clock input. A change from low-to-high on the clock inhibit input
should only be done when the clock input is high. A buffered direct clear input
overrides all other inputs, including the clock, and sets all flip-flops to zero.
Synchronous Load
Direct Overriding Clear
Parallel to Serial Conversion
14
13
12
11
10
9
1
2
A
3
B
4
C
5
D
6
7
16
15
8
VCC
SERIAL
INPUT
SHIFT/
LOAD
H
QH
G
E
F
CLEAR
CLOCK
INHIBIT
CLOCK GND
PARALLEL
INPUT OUTPUT
PARALLEL INPUTS
PARALLEL INPUTS
SHIFT/
LOAD
SERIAL INPUT
CLOCK
INHIBIT
H
QH
G
F
E
A
B
C
D
CK
CLEAR
FUNCTION TABLE
INPUTS
OUTPUTS
QH
CLEAR
LOAD
INHIBIT
CLOCK
SERIAL
PARALLEL
INTERNAL
OUTPUT
SHIFT/
CLOCK
A . . . H
QA
L
QA0
a
H
L
QA0
QB
L
QB0
b
QAn
QAn
QB0
L
H
H
H
H
H
X
X
L
H
H
X
X
L
L
L
L
H
X
L
↑
↑
↑
↑
X
X
X
H
L
X
X
X
L
QH0
h
QGn
QGn
QH0
a . . . h
X
X
X
SN54/74LS166
8-BIT SHIFT REGISTERS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54LS168 | BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS |
| SN54LS168J | BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS |
| SN54LS191J | PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS |
| SN74LS190D | PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS |
| SN74LS190N | axial lead glass packaged PIN diodes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LS166ND | 制造商:Motorola Inc 功能描述: |
| SN74LS168N | 制造商:Motorola Inc 功能描述:IC,COUNTER,UP/DOWN,DECADE,LS-TTL,DIP,16PIN,PLASTIC |
| SN74LS169BD | 功能描述:計數(shù)器 IC Synch 4-Bit Up/Down Binary Counter RoHS:否 制造商:NXP Semiconductors 計數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計數(shù)法: 計數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| SN74LS169BDE4 | 功能描述:計數(shù)器 IC Synch 4-Bit Up/Down Binary Counter RoHS:否 制造商:NXP Semiconductors 計數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計數(shù)法: 計數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| SN74LS169BDG4 | 功能描述:計數(shù)器 IC Sync 4B Up Down Binary Counters RoHS:否 制造商:NXP Semiconductors 計數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計數(shù)法: 計數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
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