參數(shù)資料
型號(hào): SN74LS196N
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Demonstration Circuit Board for AMMP-6530 (Mixer)
中文描述: LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP16
封裝: PLASTIC, DIP-16
文件頁(yè)數(shù): 3/8頁(yè)
文件大?。?/td> 227K
代理商: SN74LS196N
5-374
FAST AND LS TTL DATA
SN54/74LS196
SN54/74LS197
FUNCTIONAL DESCRIPTION
The LS196 and LS197 are asynchronously presettable de-
cade and binary ripple counters. The LS196 Decade Counter
is partitioned into divide-by-two and divide-by-five sections
while the LS197 is partitioned into divide-by-two and divide-
by-eight sections, with all sections having a separate Clock in-
put. In the counting modes, state changes are initiated by the
HIGH to LOW transition of the clock signals. State changes of
the Q outputs, however, do not occur simultaneously because
of the internal ripple delays. When using external logic to de-
code the Q outputs, designers should bear in mind that the un-
equal delays can lead to decoding spikes and thus a decoded
signal should not be used as a clock or strobe. The CP0 input
serves the Q0 flip-flop in both circuit types while the CP1 input
serves the divide-by-five or divide-by-eight section. The Q0
output is designed and specified to drive the rated fan-out plus
the CP1 input. With the input frequency connected to CP0 and
Q0 driving CP1, the LS197 forms a straightforward module-16
counter, with Q0 the least significant output and Q3 the most
significant output.
The LS196 Decade Counter can be connected up to oper-
ate in two different count sequences, as indicated in the tables
of Figure 2. With the input frequency connected to CP0 and
with Q0 driving CP1, the circuit counts in the BCD (8, 4, 2, 1)
sequence. With the input frequency connected to CP1 and Q3
driving CP0, Q0 becomes the low frequency output and has a
50% duty cycle waveform. Note that the maximum counting
rate is reduced in the latter (bi-quinary) configuration because
of the interstage gating delay within the divide-by-five section.
The LS196 and LS197 have an asynchronous active LOW
Master Reset input (MR) which overrides all other inputs and
forces all outputs LOW. The counters are also asynchronously
presettable. A LOW on the Parallel Load input (PL) overrides
the clock inputs and loads the data from Parallel Data (P0–P3)
inputs into the flip-flops. While PL is LOW, the counters act as
transparent latches and any change in the Pn inputs will be re-
flected in the outputs.
Figure 2. LS196 COUNT SEQUENCES
DECADE (NOTE 1)
BI-QUINARY (NOTE 2)
COUNT
Q3
L
L
L
L
L
L
L
L
H
H
Q2
L
L
L
L
H
H
H
H
L
L
Q1
L
L
H
H
L
L
H
H
L
L
Q0
L
H
L
H
L
H
L
H
L
H
COUNT
Q0
L
L
L
L
L
H
H
H
H
H
Q3
L
L
L
L
H
L
L
L
L
H
Q2
L
L
H
H
L
L
L
H
H
L
Q1
L
H
L
H
L
L
H
L
H
L
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
NOTES:
1. Signal applied to CP0, Q0 connected to CP1.
2. Signal applied to CP1, Q3 connected to CP0.
MODE SELECT TABLE
INPUTS
RESPONSE
MR
PL
CP
L
H
H
X
L
H
X
X
Reset (Clear)
Parallel Load
Count
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
= HIGH to Low Clock Transition
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74LS197N 制造商:Texas Instruments 功能描述:
SN74LS19AD 功能描述:變換器 Hex Schmitt-Trigger 變換器 RoHS:否 制造商:NXP Semiconductors 電路數(shù)量:6 邏輯系列:74ABT 邏輯類型:BiCMOS 高電平輸出電流:- 15 mA 低電平輸出電流:20 mA 傳播延遲時(shí)間:2.2 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 工作溫度范圍: 封裝 / 箱體:DIP-14 封裝:Tube
SN74LS19ADB 制造商:Rochester Electronics LLC 功能描述:- Bulk
SN74LS19ADBR 制造商:Rochester Electronics LLC 功能描述:- Bulk
SN74LS19ADE4 功能描述:變換器 Hex Schmitt-Trigger 變換器 RoHS:否 制造商:NXP Semiconductors 電路數(shù)量:6 邏輯系列:74ABT 邏輯類型:BiCMOS 高電平輸出電流:- 15 mA 低電平輸出電流:20 mA 傳播延遲時(shí)間:2.2 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 工作溫度范圍: 封裝 / 箱體:DIP-14 封裝:Tube