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參數(shù)資料
| 型號(hào)： | SN74LS259 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | LOW POWER SCHOTTKY |
| 中文描述： | 低功耗肖特基 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 142K |
| 代理商： | SN74LS259 |
E
C
MODE
L
H
L
H
H
H
L
L
Addressable Latch
Memory
Active HIGH Eight-Channel
Demultiplexer
Clear
MODE SELECTION
X = Don’t Care Condition
L = LOW Voltage Level
H = HIGH Voltage Level
Q
N–1
= Previous Output State
SN74LS259
http://onsemi.com
3
LOGIC DIAGRAM
E
D
A
0
A
1
A
2
C
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
14
1
2
6
7
3
4
5
9
11
12
10
13
15
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The SN74LS259 has four modes of operation as shown in
the mode selection table. In the addressable latch mode, data
on the Data line (D) is written into the addressed latch.The
addressed latch will follow the data input with all
non-addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state
and are unaffected by the Data or Address inputs.
In the one-of-eight decoding or demultiplexing mode, the
addressed output will follow the state of the D input with all
other inputs in the LOW state. In the clear mode all outputs
are LOW and unaffected by the address and data inputs.
When operating the SN74LS259 as an addressable latch,
changing more then one bit of the address could impose a
transient wrong address. Therefore, this should only be done
while in the memory mode.
The truth table below summarizes the operations.
TRUTH TABLE
PRESENT OUTPUT STATES
C E D A
0
L H X
L L L
L L H
L L L
L L H
L L H
A
1
X
L
L
L
L
H
A
2
X
L
L
L
L
Q
0
L
L
H
L
L
Q
1
L
L
L
L
H
Q
2
L
L
L
L
L
Q
3
L
L
L
L
L
L
Q
4
L
L
L
L
L
Q
5
L
L
L
L
L
Q
6
L
L
L
L
L
Q
7
L
L
L
L
L
MODE
X
L
L
H
H
Clear
Demultiplex
H
H
L
L
L
L
L
L
H
H H X
X
X
X
Q
N–1
L
H
Q
N–1
Q
N–1
Memory
H I
H L H
H L L
H L H
H L L
H L H
I
L
L
H
H
L
L
L
L
H
H
L
L
L
L
Q
N–1
Q
N–1
L
H
Q
N–1
Q
N–1
Q
N–1
Q
N–1
Q
N–1
Addressable
Latch
H
H
H
H
Q
N–1
Q
N–1
Q
N–1
Q
N–1
L
H
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74LS259D | LOW POWER SCHOTTKY |
| SN74LS259N | LOW POWER SCHOTTKY |
| SN74LS260D | DUAL 5-INPUT NOR GATE |
| SN54LS260 | Octal Bidirectional Transceiver with 3-State Inputs/Outputs; Package: SOEIAJ-20; No of Pins: 20; Container: Rail; Qty per Container: 40 |
| SN54LS260J | Octal Bidirectional Transceiver with 3-State Inputs/Outputs; Package: 20 LEAD PDIP; No of Pins: 20; Container: Rail; Qty per Container: 18 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LS259B | 制造商:. 功能描述: |
| SN74LS259BD | 功能描述:閉鎖 Octal addressable 閉鎖 RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LS259BDE4 | 功能描述:閉鎖 Octal addressable 閉鎖 RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LS259BDG4 | 功能描述:閉鎖 Octal addressable latches RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| SN74LS259BDR | 功能描述:閉鎖 Octal addressable 閉鎖 RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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