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參數(shù)資料
| 型號： | SN74LS259N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-BIT ADDRESSABLE LATCH |
| 中文描述： | LS SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 217K |
| 代理商： | SN74LS259N |
E
C
MODE
L
H
L
H
H
H
L
L
Addressable Latch
Memory
Active HIGH Eight-Channel
Demultiplexer
Clear
MODE SELECTION
X = Don’t Care Condition
L = LOW Voltage Level
H = HIGH Voltage Level
QN–1 = Previous Output State
5-434
FAST AND LS TTL DATA
SN54/74LS259
LOGIC DIAGRAM
FUNCTIONAL DESCRIPTION
The SN54/74LS259 has four modes of operation as shown
in the mode selection table. In the addressable latch mode,
data on the Data line (D) is written into the addressed
latch.The addressed latch will follow the data input with all
non-addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state
and are unaffected by the Data or Address inputs.
In the one-of-eight decoding or demultiplexing mode, the
addressed output will follow the state of the D input with all
other inputs in the LOW state. In the clear mode all outputs are
LOW and unaffected by the address and data inputs.
When operating the SN54/74LS259 as an addressable
latch, changing more then one bit of the address could impose
a transient wrong address. Therefore, this should only be
done while in the memory mode.
The truth table below summarizes the operations.
TRUTH TABLE
PRESENT OUTPUT STATES
C E D A0
L H X
L L L
L L H
L L L
L L H
L L H
A1
X
L
L
L
L
H
A2
X
L
L
L
L
Q0
L
L
H
L
L
Q1
L
L
L
L
H
Q2
L
L
L
L
L
Q3
L
L
L
L
L
L
Q4
L
L
L
L
L
Q5
L
L
L
L
L
Q6
L
L
L
L
L
Q7
L
L
L
L
L
MODE
X
L
L
H
H
Clear
Demultiplex
H
H
L
L
L
L
L
L
H
H H X
X
X
X
QN–1
L
H
QN–1
QN–1
Memory
H I
H L H
H L L
H L H
H L L
H L H
I
L
L
H
H
L
L
L
L
H
H
L
L
L
L
QN–1
QN–1
L
H
QN–1
QN–1
QN–1
QN–1
QN–1
Addressable
Latch
H
H
H
H
QN–1
QN–1
QN–1
QN–1
L
H
相關PDF資料 |
PDF描述 |
|---|---|
| SN54LS279 | 8-Bit Addressable Latch; Package: SOEIAJ-16; No of Pins: 16; Container: Rail; Qty per Container: 50 |
| SN74LS279D | QUAD SET-RESET LATCH |
| SN74LS279N | QUAD SET-RESET LATCH |
| SN54LS279J | Octal D-Type Flip-Flop; Package: SOIC-20 WB; No of Pins: 20; Container: Rail; Qty per Container: 38 |
| SN54LS283 | Quad 2-Input OR Gate; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LS259ND | 制造商:TI 功能描述:74LS259 S10L1B |
| SN74LS2600D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74LS260N | 制造商:Motorola 功能描述:74LS260 MOT'93 |
| SN74LS261D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74LS266D | 功能描述:邏輯門 Quad 2 Input RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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