- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376415 > SN74LS293 (Motorola, Inc.) 3V LNA, 4.5mA Low Current, 0.5-4GHz, SOT363(SC-70) PDF資料下載
參數(shù)資料
| 型號(hào)： | SN74LS293 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 3V LNA, 4.5mA Low Current, 0.5-4GHz, SOT363(SC-70) |
| 中文描述： | 十進(jìn)制計(jì)數(shù)器，4位二進(jìn)制計(jì)數(shù)器 |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大小： | 205K |
| 代理商： | SN74LS293 |
5-468
FAST AND LS TTL DATA
SN54/74LS290 SN54/74LS293
FUNCTIONAL DESCRIPTION
The LS290 and LS293 are 4-bit ripple type Decade, and
4-Bit Binary counters respectively. Each device consists of
four master/slave flip-flops which are internally connected to
provide a divide-by-two section and a divide-by-five (LS290)
or divide-by-eight (LS293) section. Each section has a
separate clock input which initiates state changes of the
counter on the HIGH-to-LOW clock transition. State changes
of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used for clocks
or strobes. The Q0 output of each device is designed and
specified to drive the rated fan-out plus the CP1 input of the
device.
A gated AND asynchronous Master Reset (MR1
MR2) is
provided on both counters which overrides the clocks and
resets (clears) all the flip-flops. A gated AND asynchronous
Master Set (MS1
MS2) is provided on the LS290 which
overrides the clocks and the MR inputs and sets the outputs to
nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices
may be operated in various counting modes:
LS290
A. BCD Decade (8421) Counter — the CP1 input must be
externally connected to the Q0 output. The CP0 input
receives the incoming count and a BCD count sequence is
produced.
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3
output must be externally connected to the CP0 input. The
input count is then applied to the CP1 input and a
divide-by-ten square wave is obtained at output Q0.
C. Divide-By-Two and Divide-By-Five Counter — No external
interconnections are required. The first flip-flop is used as a
binary element for the divide-by-two function (CP0 as the
input and Q0 as the output). The CP1 input is used to obtain
binary divide-by-five operation at the Q3 output.
LS293
A. 4-Bit Ripple Counter — The output Q0 must be externally
connected to input CP1. The input count pulses are applied
to input CP0. Simultaneous division of 2, 4, 8, and 16 are
performed at the Q0, Q1, Q2, and Q3 outputs as shown in
the truth table.
B. 3-Bit Ripple Counter — The input count pulses are applied
to input CP1. Simultaneous frequency divisions of 2, 4, and
8 are available at the Q1, Q2, and Q3 outputs. Independent
use of the first flip-flop is available if the reset function
coincides with reset of the 3-bit ripple-through counter.
LS290 MODE SELECTION
RESET/SET INPUTS
OUTPUTS
MR1
H
H
X
L
X
L
X
MR2
H
H
X
X
L
X
L
MS1
L
X
H
L
X
X
L
MS2
X
L
H
X
L
L
X
Q0
L
L
H
Q1
L
L
L
Q2
L
L
L
Q3
L
L
H
Count
Count
Count
Count
LS290
BCD COUNT SEQUENCE
COUNT
OUTPUT
Q1
L
L
H
H
L
L
H
H
L
L
Q0
L
H
L
H
L
H
L
H
L
H
Q2
L
L
L
L
H
H
H
H
L
L
Q3
L
L
L
L
L
L
L
L
H
H
0
1
2
3
4
5
6
7
8
9
NOTE: Output Q0 is connected to Input CP1
for BCD count.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
LS293 MODE SELECTION
RESET INPUTS
OUTPUTS
MR1
H
L
H
L
MR2
H
H
L
L
Q0
L
Q1
L
Q2
L
Q3
L
Count
Count
Count
TRUTH TABLE
COUNT
OUTPUT
Q0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Q1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
Q2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
Q3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Note: Output Q0 connected to input CP1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54LS293J | DECADE COUNTER; 4-BIT BINARY COUNTER |
| SN74LS293D | DECADE COUNTER; 4-BIT BINARY COUNTER |
| SN74LS293N | DECADE COUNTER; 4-BIT BINARY COUNTER |
| SN74LS298D | QUAD 2-INPUT MULTIPLEXER WITH STORAGE |
| SN74LS298N | >6V Fixed Gain, 10 dBm General Purpose Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LS293D | 功能描述:計(jì)數(shù)器 IC 4-BIT BINARY COUNTERS RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| SN74LS293DE4 | 功能描述:計(jì)數(shù)器 IC 4-BIT BINARY COUNTERS RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| SN74LS293DG4 | 功能描述:計(jì)數(shù)器 IC 4B Binary Counter RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| SN74LS293DR | 功能描述:計(jì)數(shù)器移位寄存器 4-BIT BINARY COUNTERS RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| SN74LS293DRE4 | 功能描述:計(jì)數(shù)器 IC 4-BIT BINARY COUNTERS RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。