參數(shù)資料
型號: SN74LS298N
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: >6V Fixed Gain, 10 dBm General Purpose Amplifier
中文描述: LS SERIES, NEGATIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 3/6頁
文件大?。?/td> 187K
代理商: SN74LS298N
5-475
FAST AND LS TTL DATA
SN54/74LS298
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
74
0.8
VIK
Input Clamp Diode Voltage
–0.65
–1.5
V
VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54
2.5
3.5
V
or VIL per Truth Table
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
per Truth Table
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
IIH
Input HIGH Current
20
μ
A
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
0.1
mA
IIL
IOS
ICC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
Input LOW Current
–0.4
mA
Short Circuit Current (Note 1)
–20
–100
mA
Power Supply Current
21
mA
AC CHARACTERISTICS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
tPHL
Propagation Delay,
Clock to Output
18
27
ns
CL = 15 pF
tPLH
21
32
ns
VCC = 5.0 V,
AC SET-UP REQUIREMENTS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
tW
ts
ts
th
th
Clock Pulse Width
20
ns
VCC = 5.0 V
Data Setup Time
15
ns
Select Setup Time
25
ns
Data Hold Time
5.0
ns
Select Hold Time
0
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW to HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW to
HIGH and still be recognized.
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