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參數(shù)資料
| 型號： | SN74LS323DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS |
| 中文描述： | LS SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 143K |
| 代理商： | SN74LS323DW |
5-2
FAST AND LS TTL DATA
SN54/74LS323
LOGIC DIAGRAM
S1
S0
DS0
SR
Q0
OE1
OE2
D
Q
CP
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DS7
Q7
14
1
2
6
7
3
8
4
5
9
11
12
13
15
16
17
18
19
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
CP
FUNCTIONAL DESCRIPTION
The logic diagram and truth table indicate the functional
characteristics of the SN54/74LS323 Universal Shift/Storage
Register. This device is similar in operation to the
SN54/74LS299 except for synchronous reset. A partial list of
the common features are described below:
1. They use eight D-type edge-triggered flip-flops that re-
spond only to the LOW-to-HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control (S0, S1) and data inputs (DS0, DS7, I/O0–I/O7) may
be stable at least a setup time prior to the positive transition
of the Clock Pulse.
2. When S0 = S1 = 1, I/O0–I/O7 are parallel inputs to flip-flops
Q0–Q7 respectively, and the outputs of Q0–Q7 are in the
high impedance state regardless of the state of OE1 or
OE2.
An important unique feature of the SN54/74LS323 is a fully
Synchronous Reset that requires only to be stable at least one
setup time prior to the positive transition of the Clock Pulse.
TRUTH TABLE
INPUTS
RESPONSE
SR
S1
X
X
H
S0
X
X
H
OE1
H
X
X
OE2
X
H
X
CP
DS0
X
X
X
DS7
X
X
X
L
L
L
I/O voltage undetermined
Synchronous Reset; Q0 = Q7 = LOW
L
L
L
X
X
L
L
L
L
L
X
X
X
X
Synchronous Reset; Q0 = Q7 = LOW
I/O voltage LOW
H
H
L
L
H
H
X
L
X
L
D
D
X
X
Shift Right; D
o
Q0; Q0
o
Q1; etc.
Shift Right; D
o
Q0 & I/O0; Q0
o
Q1 & I/O1; etc.
Shift Left; D
o
Q7; Q7
o
Q6; etc.
Shift Left; D
o
Q7 & I/O7; Q7
o
Q6 & I/O6; etc.
Parallel Load I/On
o
Qn
H
H
H
H
L
L
X
L
X
L
X
X
D
D
H
H
H
X
X
X
X
H
H
L
L
L
L
H
X
X
H
X
X
X
X
X
X
Hold; I/O Voltage Undetermined
H
L
L
L
L
X
X
X
Hold; I/On = Qn
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LS323DWR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74LS323N | 制造商:Motorola Inc 功能描述: 制造商:ON Semiconductor 功能描述: 制造商:Texas Instruments 功能描述: |
| SN74LS323N3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74LS32D | 功能描述:邏輯門 Quad 2-input Positive-OR gates RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| SN74LS32DBLE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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