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參數(shù)資料
| 型號： | SN74LS353N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS |
| 中文描述： | LS SERIES, DUAL 4 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 192K |
| 代理商： | SN74LS353N |
5-511
FAST AND LS TTL DATA
SN54/74LS353
LOGIC DIAGRAM
FUNCTIONAL DESCRIPTION
The SN54/74LS353 contains two identical 4-input Multi-
plexers with 3-state outputs. They select two bits from four
sources selected by common select inputs (S0, S1). The
4-input multiplexers have individual Output Enable (E0a, E0b)
inputs which when HIGH, forces the outputs to a high
impedance (high Z) state.
The logic equations for the outputs are shown below:
Za = E0a
(I0a
S1
S0 + I1a
S1
S0 + I2a
S1
S0 + I3a
S1
S0)
Zb = E0b
(I0b
S1
S0 + I1b
S1
S0 + I2b
S1
S0 + I3b
S1
S0)
If the outputs of 3-state devices are tied together, all but one
device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so that there is
no overlap.
TRUTH TABLE
SELECT
INPUTS
DATA INPUTS
OUTPUT
ENABLE
OUTPUT
S0
X
L
L
H
H
L
L
H
H
S1
X
L
L
L
L
H
H
H
H
I0
X
L
H
X
X
X
X
X
X
I1
X
X
X
L
H
X
X
X
X
I2
X
X
X
X
X
L
H
X
X
I3
X
X
X
X
X
X
X
L
H
E0
H
L
L
L
L
L
L
L
L
Z
(Z)
H
L
H
L
H
L
H
L
H = HIGH Level
L = LOW Level
X = Immaterial
(Z) = High Impedance (off)
Address inputs S0 and S1 are common to both sections.
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