參數(shù)資料
型號: SN74LS77
廠商: Motorola, Inc.
英文描述: 4-BIT D LATCH LOW POWER SCHOTTKY
中文描述: 4位D鎖存低功耗肖特基
文件頁數(shù): 4/4頁
文件大?。?/td> 71K
代理商: SN74LS77
5-4
FAST AND LS TTL DATA
SN54/74LS75 SN54/74LS77
LOGIC DIAGRAM
DATA
ENABLE
TO OTHER LATCH
Q (SN54/74LS75 ONLY)
Q
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°
C
IOH
IOL
Output Current — High
54, 74
–0.4
mA
Output Current — Low
54
74
4.0
8.0
mA
AC SETUP REQUIREMENTS
(TA = 25
°
C, VCC = 5.0 V)
Symbol
b l
Parameter
Limits
U i
Unit
Test Conditions
di i
Min
Typ
Max
tW
ts
th
Enable Pulse Width High
20
ns
VCC = 5.0 V
5 0 V
Setup Time
20
ns
Hold Time
0
ns
AC WAVEFORMS
D
E
Q
Q
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
th
ts
tPLH
tPLH
tPHL
tPHL
tPLH
tPHL
tPHL
tPLH
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the
clock transition from HIGH-to-LOW in order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH-to-LOW that the logic level must be
maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may
be released prior to the clock transition from HIGH-to-LOW and still be recognized.
相關PDF資料
PDF描述
SN74LS798DW TRI-STATE OCTAL BUFFERS
SN54LS795 8-Bit Serial or Parallel-Input/Serial Output Shift Register; Package: PDIP-16; No of Pins: 16; Container: Rail; Qty per Container: 500
SN54LS795J Hex D-Type Flip-Flop with Clock; Package: SOIC 16 LEAD; No of Pins: 16; Container: Rail; Qty per Container: 48
SN54LS796 Hex D-Type Flip-Flop with Clock; Package: SOIC 16 LEAD; No of Pins: 16; Container: Tape and Reel; Qty per Container: 2500
SN54LS796J Hex D-Type Flip-Flop with Clock; Package: SOIC 16 LEAD; No of Pins: 16; Container: Tape and Reel; Qty per Container: 2500
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