參數(shù)資料
型號: SN74LV125APWG4
廠商: Texas Instruments
文件頁數(shù): 12/24頁
文件大小: 0K
描述: IC BUS BUFF TRI-ST QUAD 14TSSOP
標準包裝: 90
系列: 74LV
邏輯類型: 緩沖器/線路驅(qū)動器,非反相
元件數(shù): 4
每個元件的位元數(shù): 1
輸出電流高,低: 16mA,16mA
電源電壓: 2 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 14-TSSOP
包裝: 管件
SN54LV125A, SN74LV125A
QUADRUPLE BUS BUFFER GATES
WITH 3STATE OUTPUTS
SCES124L DECEMBER 1997 REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE
A
OUTPUT
Y
L
H
L
LL
H
X
Z
logic diagram (positive logic)
2A
2Y
2OE
1A
1Y
1OE
1
2
4
5
3
6
4A
4Y
4OE
3A
3Y
3OE
10
9
13
12
8
11
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
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