參數(shù)資料
型號(hào): SN74LV138APWT
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 編、解碼器及復(fù)用、解復(fù)用
英文描述: LV/LV-A/LVX/H SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16
封裝: GREEN, PLASTIC, TSSOP-16
文件頁(yè)數(shù): 12/22頁(yè)
文件大小: 766K
代理商: SN74LV138APWT
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
SN54LV138A, SN74LV138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS395L – APRIL 1998 – REVISED AUGUST 2005
These devices are designed for high-performance memory-decoding or data-routing applications requiring very
short propagation delay times. In high-performance memory systems, these decoders can be used to minimize
the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the
delay times of these decoders and the enable time of the memory usually are less than the typical access time of
the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1, G2A, G2B) select one of
eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for
external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters
and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing
applications.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
G1
G2A
G2B
C
B
A
Y0
Y1
Y20
Y3
Y4
Y5
Y6
Y7
X
H
X
H
X
H
X
H
L
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
2
相關(guān)PDF資料
PDF描述
SN74LV138ARGYR LV/LV-A/LVX/H SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PQCC16
SNJ54LV157AW LV/LV-A/LVX/H SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, CDFP16
SNJ54LV161AJ LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16
SN74LV161ADRG4 LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
SNJ54LV163AJ LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74LV138APWTE4 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3 to 8-Line Decdr/Demltplxer RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線(xiàn)路數(shù)量(輸入/輸出):2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
SN74LV138APWTG4 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3 to 8-Line Decdr/Demltplxer RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線(xiàn)路數(shù)量(輸入/輸出):2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
SN74LV138ARGYR 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 Line Decoder RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線(xiàn)路數(shù)量(輸入/輸出):2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
SN74LV138ARGYRG4 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3 to 8-Line Decdr/Demltplxer RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線(xiàn)路數(shù)量(輸入/輸出):2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
SN74LV138ATD 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3Ln To 8Ln Decoder Demultiplexers RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線(xiàn)路數(shù)量(輸入/輸出):2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray