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參數(shù)資料
| 型號： | SN74LV174ADGVRG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HEX D-TYPE FLIP-FLOPS WITH CLEAR |
| 中文描述： | 六角D型倒裝，沒有明確的觸發(fā)器 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 416K |
| 代理商： | SN74LV174ADGVRG4 |
SN54LV174A, SN74LV174A
HEX DTYPE FLIPFLOPS
WITH CLEAR
SCLS401G APRIL 1998 REVISED APRIL 2005
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
SN54LV174A
SN74LV174A
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration
CLR low
6
6.5
ns
tw
Pulse duration
CLK high or low
7
ns
tsu
Setup time before CLK
↑
Data
8.5
9.5
ns
tsu
Setup time before CLK
↑
CLR inactive
4
ns
th
Hold time, data after CLK
↑
0.5
0
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
SN54LV174A
SN74LV174A
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration
CLR low
5
ns
tw
Pulse duration
CLK high or low
5
ns
tsu
Setup time before CLK
↑
Data
5
6
ns
tsu
Setup time before CLK
↑
CLR inactive
3
ns
th
Hold time, data after CLK
↑
0
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
SN54LV174A
SN74LV174A
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration
CLR low
5
ns
tw
Pulse duration
CLK high or low
5
ns
tsu
Setup time before CLK
↑
Data
4.5
ns
tsu
Setup time before CLK
↑
CLR inactive
2.5
ns
th
Hold time, data after CLK
↑
0.5
ns
switching
characteristics
over
recommended
operating
free-air
temperature
range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25°C
SN54LV174A
SN74LV174A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
CL = 15 pF
55*
115*
50*
50
MHz
fmax
CL = 50 pF
45
90
40
MHz
tpd
CLR
Q
CL = 15 pF
6.3*
17.3*
1*
19.5*
1
19.5
ns
tpd
CLK
Q
CL = 15 pF
8.4*
17.1*
1*
19*
1
19
ns
tpd
CLR
Q
8.2
21.9
1
23.5
1
23.5
tpd
CLK
Q
CL = 50 pF
10.8
20.6
1
23
1
23
ns
tsk(o)
CL = 50 pF
2
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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| SN74LV174ADGVR | HEX D-TYPE FLIP-FLOPS WITH CLEAR |
| SN74LV174ADRE4 | HEX D-TYPE FLIP-FLOPS WITH CLEAR |
| SN74LV174ADRG4 | HEX D-TYPE FLIP-FLOPS WITH CLEAR |
| SN74LV174ADR | HEX D-TYPE FLIP-FLOPS WITH CLEAR |
| SN74LV174ANSRG4 | HEX D-TYPE FLIP-FLOPS WITH CLEAR |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LV174ADR | 功能描述:觸發(fā)器 Hex D-Type Flip-Flop With Clear RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| SN74LV174ADRE4 | 功能描述:觸發(fā)器 Hex D-Type Flip-Flop With Clear RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| SN74LV174ADRG4 | 功能描述:觸發(fā)器 Hex DType FlipFlop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| SN74LV174ANS | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| SN74LV174ANSR | 功能描述:觸發(fā)器 Hex D-Type Flip-Flop With Clear RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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