參數(shù)資料
型號: SN74LVC10ADBR
廠商: TEXAS INSTRUMENTS INC
元件分類: 門電路
英文描述: LVC/LCX/Z SERIES, TRIPLE 3-INPUT NAND GATE, PDSO14
封裝: GREEN, PLASTIC, SSOP-14
文件頁數(shù): 12/19頁
文件大?。?/td> 721K
代理商: SN74LVC10ADBR
www.ti.com
Y
A
B
C
Absolute Maximum Ratings
(1)
SN74LVC10A
TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284O – JANUARY 1993 – REVISED JULY 2005
FUNCTION TABLE
(EACH GATE)
INPUTS
OUTPUT
Y
A
B
C
H
L
X
H
X
L
X
H
X
L
H
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range(2)
–0.5
6.5
V
VO
Output voltage range(2)(3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
D package (4)
86
DB package(4)
96
θ
JA
Package thermal impedance
NS package(4)
76
°C/W
PW package(4)
113
RGY package(5)
47
Tstg
Storage temperature range
–65
150
°C
Ptot
Power dissipation
TA = –40°C to 125°C(6)(7)
500
mW
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The value of VCC is provided in the recommended operating conditions table.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
(5)
The package thermal impedance is calculated in accordance with JESD 51-5.
(6)
For the D package: above 70
°C, the value of P
tot derates linearly with 8 mW/K.
(7)
For the DB, NS, and PW packages: above 60
°C, the value of P
tot derates linearly with 5.5 mW/K.
2
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