參數(shù)資料
型號(hào)： SN74LVC138ADBLE
廠商： TEXAS INSTRUMENTS INC
元件分類： 編、解碼器及復(fù)用、解復(fù)用
英文描述： LVC/LCX/Z SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16
封裝： PLASTIC, SSOP-16
文件頁數(shù)： 12/29頁
文件大?。?/td> 1083K
代理商： SN74LVC138ADBLE
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
GQN OR ZQN PACKAGE
(TOP VIEW)
1
2
3
4
A
B
C
D
E
SN54LVC138A, SN74LVC138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS291T – MARCH 1993 – REVISED JULY 2005
The 'LVC138A devices are designed for high-performance memory-decoding or data-routing applications
requiring very short propagation delay times. In high-performance memory systems, these decoders minimize the
effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times
of these decoders and the enable time of the memory usually are less than the typical access time of the
memory. This means that the effective system delay introduced by the decoders is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only
one inverter. An enable input can be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
TERMINAL ASSIGNMENTS
1
2
3
4
A
B
A
VCC
Y0
B
C
NC(1)
Y1
C
G2B
G2A
Y3
Y2
D
G1
NC(1)
Y4
E
GND
Y7
Y6
Y5
(1)
NC - No internal connection
SDFGDFGDFG
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
G1
G2A
G2B
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
H
X
H
X
H
X
H
L
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
2
相關(guān)PDF資料
PDF描述
SN74LVC138APW LVC/LCX/Z SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16
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SN74LVC14AMDREP LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14
SN74LVC14ARGYRG4 LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PQCC14
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74LVC138ADBR 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 Line Decoder RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
SN74LVC138ADBRE4 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3-Line to 8-Line Decoder/Demltplxr RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
SN74LVC138ADBRG4 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3 Ln To 8 Ln Decodr Demultplxr RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
SN74LVC138ADE4 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3-Line to 8-Line Decoder/Demltplxr RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
SN74LVC138ADG4 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3-Line to 8-Line Decoder/Demltplxr RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
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