- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98124 > SN74LVC2G74DCTRE4 (TEXAS INSTRUMENTS INC) LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8 PDF資料下載
參數(shù)資料
| 型號(hào)： | SN74LVC2G74DCTRE4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 鎖存器 |
| 英文描述： | LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8 |
| 封裝： | GREEN, PLASTIC, MO-187DA, SSOP-8 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 536K |
| 代理商： | SN74LVC2G74DCTRE4 |
www.ti.com
FEATURES
Seemechanicaldrawingsfordimensions.
DCTPACKAGE
(TOP VIEW)
DCUPACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOMVIEW)
1
V
CC
8
CLK
2
7
D
PRE
3
6
Q
CLR
4
5
GND
Q
3
6
CLR
Q
8
1
V
CC
CLK
5
GND
4
Q
2
7
PRE
D
GND
5
4
Q
3 6
CLR
Q
2 7
PRE
D
8
V
CC
1
CLK
DESCRIPTION/ORDERING INFORMATION
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES203M – APRIL 1999 – REVISED FEBRUARY 2007
Available in the Texas Instruments
Typical V
OHV (Output VOH Undershoot)
NanoFree Package
>2 V at VCC = 3.3 V, TA = 25°C
Supports 5-V V
CC Operation
I
off Supports Partial-Power-Down Mode
Operation
Inputs Accept Voltages to 5.5 V
Latch-Up Performance Exceeds 100 mA Per
Max t
pd of 5.9 ns at 3.3 V
JESD 78, Class II
Low Power Consumption, 10-A Max I
CC
ESD Protection Exceeds JESD 22
±24-mA Output Drive at 3.3 V
–
2000-V Human-Body Model (A114-A)
Typical V
OLP (Output Ground Bounce)
–
200-V Machine Model (A115-A)
<0.8 V at V
CC = 3.3 V, TA = 25°C
–
1000-V Charged-Device Model (C101)
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
NanoFree – WCSP (DSBGA)
Reel of 3000
SN74LVC2G74YZPR
_ _ _CP_
0.23-mm Large Bump – YZP (Pb-free)
SSOP – DCT
Reel of 3000
SN74LVC2G74DCTR
C74_ _ _
–40
°C to 85°C
Reel of 3000
SN74LVC2G74DCUR
VSSOP – DCU
C74_
Reel of 250
SN74LVC2G74DCUT
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2)
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 1999–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74LVC2G74DCUR | LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8 |
| SN74LVC2GU04YEPR | LVC/LCX/Z SERIES, DUAL 1-INPUT INVERT GATE, PBGA6 |
| SN74LVC2T45DCUT | LVC/LCX/Z SERIES, 2-BIT TRANSCEIVER, TRUE OUTPUT, PDSO8 |
| SN74LVC32244ZKER | LVC/LCX/Z SERIES, OCTAL 4-BIT DRIVER, TRUE OUTPUT, PBGA96 |
| SN74LVC32373AZKER | LVC/LCX/Z SERIES, QUAD 8-BIT DRIVER, TRUE OUTPUT, PBGA96 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LVC2G74DCTRE6 | 制造商:Texas Instruments 功能描述: |
| SN74LVC2G74DCTRG4 | 功能描述:觸發(fā)器 Sgl Pos-Edge-Trgrd D-Type Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| SN74LVC2G74DCUR | 功能描述:觸發(fā)器 Positive Edge Trig RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| SN74LVC2G74DCUR | 制造商:Texas Instruments 功能描述:Flip Flop Logic IC Leaded Process Compat |
| SN74LVC2G74DCURE4 | 功能描述:觸發(fā)器 Single D-Type Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。