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參數(shù)資料
| 型號(hào)： | SN74LVC2T45DCUT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, 2-BIT TRANSCEIVER, TRUE OUTPUT, PDSO8 |
| 封裝： | GREEN, PLASTIC, VSSOP-8 |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 607K |
| 代理商： | SN74LVC2T45DCUT |
www.ti.com
APPLICATION INFORMATION
VCC1
VCC2
SYSTEM-1
SYSTEM-2
1
2
3
4
8
7
6
5
DIR CTRL
I/O-1
Pullup/Down
or Bus Hold(1)
VCC2
I/O-2
Pullup/Down
or Bus Hold(1)
Enable Times
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES516I – DECEMBER 2003 – REVISED MARCH 2007
Figure 3 shows the SN74LVC2T45 being used in a bidirectional logic level-shifting application. Since the
SN74LVC2T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
The following table shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to
SYSTEM-1.
STATE
DIR CTRL
I/O-1
I/O-2
DESCRIPTION
1
H
Out
In
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The
2
H
Hi-Z
bus-line state depends on pullup or pulldown.(1)
DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or
3
L
Hi-Z
pulldown.(1)
4
L
In
Out
SYSTEM-2 data to SYSTEM-1
(1)
SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
Figure 3. Bidirectional Logic Level-Shifting Application
Calculate the enable times for the SN74LVC2T45 using the following formulas:
t
PZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
t
PZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
t
PZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
t
PZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74LVC2T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
16
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74LVC2T45DCUT | 制造商:Texas Instruments 功能描述:Transceiver IC |
| SN74LVC2T45DCUTE4 | 功能描述:轉(zhuǎn)換 - 電壓電平 Dual Bit Dual Supply Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74LVC2T45DCUTG4 | 功能描述:轉(zhuǎn)換 - 電壓電平 Dual Bit Dual Supply Transceiver RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74LVC2T45MDCTTEP | 功能描述:轉(zhuǎn)換 - 電壓電平 EP DUALB DUAL- SUPPLY BUS Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74LVC2T45QDCURQ1 | 功能描述:轉(zhuǎn)換 - 電壓電平 AC DualB Dual Supply Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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