參數(shù)資料
型號： SN75C1154NSRE4
廠商： TEXAS INSTRUMENTS INC
元件分類： Buffer和線驅動
英文描述： QUAD LINE TRANSCEIVER, PDSO20
封裝： GREEN, PLASTIC, SOP-20
文件頁數(shù)： 12/16頁
文件大?。?/td> 498K
代理商： SN75C1154NSRE4
SN65C1154, SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D – DECEMBER 1988 – REVISED APRIL 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DRIVER SECTION
electrical characteristics over operating free-air temperature range, VDD = 12 V, VSS = –12 V,
VCC = 5 V ±10% (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High level output voltage
VIL = 0.8 V,
RL = 3 k,
VDD = 5 V,
VSS = –5 V
4
4.5
V
VOH
High-level output voltage
IL
,
See Figure 1
L
,
VDD = 12 V,
VSS = –12 V
10
10.8
V
VOL
Low-level output voltage
VIH = 2 V,
RL = 3 k,
VDD = 5 V,
VSS = –5 V
–4.4
–4
V
VOL
g
(see Note 4)
IH
,
See Figure 1
L
,
VDD = 12 V,
VSS = –12 V
–10.7
–10
V
IIH
High-level input current
VI = 5 V,
See Figure 2
1
A
IIL
Low-level input current
VI = 0,
See Figure 2
–1
A
IOS(H)
High-level short-circuit
VI =0 8V
VO =0orVSS
See Figure 1
75
12
19 5
mA
IOS(H)
g
output current
VI = 0.8 V,
VO = 0 or VSS,
See Figure 1
–7.5
–12
–19.5
mA
IOS(L)
Low-level short-circuit
VI =2V
VO =0orVDD
See Figure 1
75
12
19 5
mA
IOS(L)
output current
VI = 2 V,
VO = 0 or VDD,
See Figure 1
7.5
12
19.5
mA
IDD
Supply current from VDD
No load,
VDD = 5 V,
VSS = –5 V
115
250
A
IDD
Supply current from VDD
No load,
All inputs at 2 V or 0.8 V
VDD = 12 V,
VSS = –12 V
115
250
A
ISS
Supply current from VSS
No load,
VDD = 5 V,
VSS = –5 V
–115
–250
A
ISS
Supply current from VSS
No load,
All inputs at 2 V or 0.8 V
VDD = 12 V,
VSS = –12 V
–115
–250
A
ro
Output resistance
VDD = VSS = VCC = 0,
VO = –2 V to 2 V,
See Note 5
300
400
All typical values are at TA = 25°C.
Not more than one output should be shorted at one time.
NOTES:
4. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only.
5. Test conditions are those specified by TIA/EIA-232-F.
switching characteristics, VDD = 12 V, VSS = –12 V, VCC = 5 V ±10%, TA = 25°C (see Figure 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low- to high-level output§
RL = 3 to 7 k,
CL = 15 pF
1.2
3
s
tPHL
Propagation delay time, high- to low-level output§
RL = 3 to 7 k,
CL = 15 pF
2.5
3.5
s
tTLH
Transition time, low- to high-level output
RL = 3 to 7 k,
CL = 15 pF
0.53
2
3.2
s
tTHL
Transition time, high- to low-level output
RL = 3 to 7 k,
CL = 15 pF
0.53
2
3.2
s
tTLH
Transition time, low- to high-level output#
RL = 3 to 7 k,
CL = 2500 pF
1
2
s
tTHL
Transition time, high- to low-level output#
RL = 3 to 7 k,
CL = 2500 pF
1
2
s
SR
Output slew rate
RL = 3 to 7 k,
CL = 15 pF
4
10
30
V/
s
§ tPHL and tPLH include the additional time due to on-chip slew rate control and are measured at the 50% points.
Measured between 10% and 90% points of output waveform
# Measured between 3 V and –3 V points of output waveform (TIA/EIA-232-F conditions) with all unused inputs tied either high or low
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