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參數(shù)資料
| 型號： | SNJ54ACT564W |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ACT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 584K |
| 代理商： | SNJ54ACT564W |
SN54ACT564, SN74ACT564
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS549B – NOVEMBER 1995 – REVISED NOVEMBER 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
VOH
VOL
0 V
Input
Output
Timing Input
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
× VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
× VCC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
VOL + 0.3 V
≈0 V
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
× VCC
Open
TEST
S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
Input
VOH – 0.3 V
1.5 V
3 V
1.5 V
3 V
50% VCC
1.5 V
3 V
50% VCC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 1 MHz, ZO = 50 , tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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