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參數(shù)資料
| 型號(hào)： | SNJ54HC590AWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 計(jì)數(shù)器 |
| 英文描述： | HC/UH SERIES, ASYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, CDFP16 |
| 封裝： | CERAMIC, DFP-16 |
| 文件頁(yè)數(shù)： | 20/23頁(yè) |
| 文件大?。?/td> | 804K |
| 代理商： | SNJ54HC590AWR |
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SN54HC590A, SN74HC590A
8BIT BINARY COUNTERS
WITH 3STATE OUTPUT REGISTERS
SCLS039F DECEMBER 1982 REVISED SEPTEMBER 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C
SN54HC590A
SN74HC590A
UNIT
VCC
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
4
2.5
3.2
fclock
Clock frequency
4.5 V
20
13
16
MHz
fclock
Clock frequency
6 V
24
16
19
MHz
2 V
125
200
155
CCLK or RCLK high or low
4.5 V
25
38
31
tw
Pulse duration
CCLK or RCLK high or low
6 V
21
32
26
ns
tw
Pulse duration
2 V
100
150
125
ns
CCLR low
4.5 V
20
30
25
CCLR low
6 V
17
26
21
2 V
100
150
125
CCKEN low before CCLK
↑
4.5 V
20
30
25
CCKEN low before CCLK
↑
6 V
17
26
21
2 V
100
150
125
tsu
Setup time
CCLR high (inactive) before CCLK
↑
4.5 V
20
30
25
ns
tsu
Setup time
CCLR high (inactive) before CCLK
↑
6 V
17
26
21
ns
2 V
100
150
125
CCLK
↑ before RCLK↑
4.5 V
20
30
25
CCLK
↑ before RCLK↑
6 V
17
26
21
2 V
50
75
60
th
Hold time
CCKEN low after CCLK
↑
4.5 V
10
15
12
ns
th
Hold time
CCKEN low after CCLK
6 V
9
13
11
ns
This setup time ensures that the register gets stable data from the counter outputs. The clocks may be tied together, in which case the register
is one clock pulse behind the counter.
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| SNJ54HC590AJ | HC/UH SERIES, ASYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, CDIP16 |
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| SN74HC590ADTG4 | HC/UH SERIES, ASYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PDSO16 |
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