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參數(shù)資料
| 型號： | SNJ54LV123AW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS |
| 中文描述： | 雙RETRIGGERABLE單穩(wěn)多諧振蕩器與施密特觸發(fā)輸入 |
| 文件頁數(shù)： | 1/23頁 |
| 文件大?。?/td> | 535K |
| 代理商： | SNJ54LV123AW |
SCLS393O APRIL 1998 REVISED OCTOBER 2005
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2-V to 5.5-V V
CC
Operation
Max t
pd
of 11 ns at 5 V
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
>2.3 V at V
CC
= 3.3 V, T
A
= 25
°
C
Support Mixed-Mode Voltage Operation on
All Ports
Schmitt-Trigger Circuitry on A, B, and CLR
Inputs for Slow Input Transition Rates
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
I
off
Supports Partial-Power-Down Mode
Operation
Retriggerable for Very Long Output Pulses,
up to 100% Duty Cycle
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset on Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
SN54LV123A . . . J OR W PACKAGE
SN74LV123A . . . D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
SN54LV123A . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1B
1CLR
1Q
2Q
2C
ext
2R
ext
/C
ext
GND
V
CC
1R
ext
/C
ext
1C
ext
1Q
2Q
2CLR
2B
2A
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
1C
ext
1Q
NC
2Q
2CLR
1CLR
1Q
NC
2Q
2C
ext
1
1
N
2
2
V
1
2
G
N
C
NC No internal connection
e
/
e
e
/
e
SN74LV123A . . . RGY PACKAGE
(TOP VIEW)
1
16
8
9
2
3
4
5
6
7
15
14
13
12
11
10
1R
ext
/C
ext
1C
ext
1Q
2Q
2CLR
2B
1B
1CLR
1Q
2Q
2C
ext
2R
ext
/C
ext
1
2
V
G
description/ordering information
The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V V
CC
operation.
These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method,
the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low.
In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse
duration
is programmable by selecting external resistance and capacitance values. The
external timing capacitor must be connected between C
ext
and R
ext
/C
ext
(positive) and an external resistor
connected between R
ext
/C
ext
and V
CC
. To obtain variable pulse durations, connect an external variable
resistance between R
ext
/C
ext
and V
CC
. The output pulse duration also can be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. The input/output timing diagram
illustrates pulse control by retriggering the inputs and early clearing.
Copyright
2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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