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參數(shù)資料
| 型號： | SNJ54LV595AWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 計數(shù)移位寄存器 |
| 英文描述： | LV/LV-A/LVX/H SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP16 |
| 封裝： | CERAMIC, FP-16 |
| 文件頁數(shù)： | 12/26頁 |
| 文件大?。?/td> | 848K |
| 代理商： | SNJ54LV595AWR |
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SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414O APRIL 1998 REVISED JANUARY 2011
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register.
The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage
register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output
for cascading. When the output-enable (OE) input is high, all outputs except QH′ are in the high-impedance
state.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
FUNCTION
SER
SRCLK SRCLR
RCLK
OE
FUNCTION
X
H
Outputs QAQH are disabled.
X
L
Outputs QAQH are enabled.
X
L
X
Shift register is cleared.
L
↑
H
X
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H
↑
H
X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
X
↑
X
Shift-register data is stored in the storage register.
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