參數(shù)資料
型號(hào): SP207CA-L/TR
廠商: Exar Corporation
文件頁(yè)數(shù): 10/14頁(yè)
文件大?。?/td> 0K
描述: IC TXRX RS232 SERIAL 24SSOP
產(chǎn)品變化通告: Interface Product Discontinuation 10/May/2011
標(biāo)準(zhǔn)包裝: 1,500
類(lèi)型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 5/3
規(guī)程: RS232
電源電壓: 4.5 V ~ 5.5 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 帶卷 (TR)
5
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (50)668-7000 Fax (50)668-707 www.exar.com SP206, 207, 208, 2_0_060
DESCRIPTION
FEATURES
The SP206/207/208/2 multi-channel RS-232
line transceivers provide a variety of configu-
rations to fit most communication needs, es-
pecially those applications where +/-2V is not
available. All models in this series feature low-
power CMOS construction and Exar's proprie-
tary on-board charge pump circuitry to generate
the +/-0V RS-232 voltage levels. The ability to
use 0.F charge pump capacitors saves board
space and reduces circuit cost. Different mod-
els within the series provide different driver/re-
ceiver combinations to match any application
requirement.
The SP206 and SP2 models feature a low-
power shutdown mode that reduces power sup-
ply drain to A.
The models in this series are available in 24-pin
and 28-pin SO (wide) and SSOP (shrink) small
outline packages. Devices can be specified for
commercial (0C to +70C) or industrial/extend-
ed (-40C to +85C) operating temperatures.
THEORY OF OPERATION
CHARgE PUMP
The charge pump is an Exar patented design
and uses a unique approach compared to older
less-efficient designs. The charge pump still
requires four external capacitors, but uses a
four phase voltage shifting technique to attain
symmetrical +/-0V power supplies. Figure a
shows the waveform found on the positive side
of capacitor C2 and Figure 3b shows the nega-
tive side of capacitor C2. There is a free-run-
ning oscillator that controls the four phases of
the voltage shifting. A description of each phase
follows:
PHASE 1
Vss charge storage - During this phase of the
clock cycle, the positive side of capacitors C
and C2 are initially charged to +5V. C+ is then
switched to ground and the charge in C- is
transferred to C2-. Since C2+ is connected to
+5V, the voltage potential across capacitor C2
is now 0V.
PHASE 2
Vss transfer: Phase two of the clock connects
the negative terminal of C2 to the Vss stor-
age capacitor and the positive terminal of C2
to ground, and transfers the generated -0V to
C3. Simultaneously, the positive side of capaci-
tor C is switched to +5V and the negative side
is connected to ground.
PHASE 3
Vdd charge storage: The third phase of the
clock is identical to the first phase. The charge
transferred in C produces -5V in the negative
terminal of C, which is applied to the negative
side of C2. Since C2+ is at +5V, the voltage po-
tential across C2 is 0V.
PHASE 4
Vdd transfer: The fourth phase of the clock con-
nects the negative terminal of C2 to ground,
and transfers the generated 0V across C2 to
C4, the Vdd storage capacitor. Again, simulta-
neously with this, the positive side of capaci-
tor C is switched to +5V and the negative side
is connected to ground, and the cycle begins
again.
Since both V+ and V- are separately generated
from Vcc; in a no-load condition V+ and V- will
be symmetrical. Older charge pump approach-
es that generate V- from V+ will show a de-
crease in magnitude of V- compared to V+ due
to the inherent inefficiencies in the design.
The clock rate for the charge pump typically op-
erates at greater than 5kHz allowing the pump
to run efficiently with small 0.1uF capacitors
with a 6V breakdown voltage rating.
The SP206/207/208/2 devices are made up
of three basic circuit blocks - ) transmitter/
driver, 2) receiver and 3) charge pump. Each
model within the series incorporates variations
of these circuit to achieve the desired configu-
ration and performance.
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