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參數(shù)資料
| 型號： | SP3203CY |
| 元件分類： | RS-232 |
| 英文描述： | 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors |
| 中文描述： | 5V的高速RS - 232收發(fā)器與0.1uF電容 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 121K |
| 代理商： | SP3203CY |
Rev. 6/25/03
SP3203
8
Copyright 2003 Sipex Corporation
consists of a regulated dual charge pump that
provides output voltages of 5.5V regardless of
the input voltage (V
CC
) over the +3.0V to +5.5V
range. This is important to maintain compliant
RS-232 levels regardless of power supply
fluctuations.
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a of 5.5V, the charge
pump is enabled. If the output voltages exceed
a of 5.5V, the charge pump is disabled. This
oscillator controls the four phases of the voltage
shifting (Figure 12). A description of each phase
follows.
V
SS
Charge Storage-Phase 1(Figure 13)
During this phase of the clock cycle, the positive
side of capacitors C
1
and C
2
are initially charged
to V
CC
. C
l+
is then switched to GND and the
charge in C
1–
is transferred to C
2–
. Since C
2+
is
connected to V
CC
, the voltage potential across
capacitor C
2
is now 2 times V
CC
.
Table 1. SHUTDOWN Truth Table.
(Note: When device in shutdown, the SP3203's charge pump is turned off
and V+ decays to V
V- is pulled to ground and the transmitter outputs
are disabled as High Impendance).
Figure 9. Loopback Test Circuit for RS-232 Driver Data
Transmission Rates
V
SS
Transfer-Phase 2 (Figure 14)
Phase two of the clock connects the negative
terminal of C
2
to the V
SS
storage capacitor and
the positive terminal of C
2
to GND. This
transfers a negative generated voltage to C
3
.
This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage
to C
3
, the positive side of capacitor C
1
is
switched to V
CC
and the negative side is
connected to GND
.
V
DD
Charge Storage-Phase 3 (Figure 15)
The third phase of the clock is identical to the
first phase — the charge transferred in C
1
pro-
Figure 10. Loopback Test Circuit Result at 120Kbps
(All Drivers Fully Loaded)
Figure 11. Loopback Test Circuit result at 250Kbps
(All Drivers Fully Loaded)
SP3203
1
3
5
4
2
6
19
GND
T
1
IN
T
X
IN
C1+
C1-
C2+
C2-
V+
V-
V
CC
0.1
μ
F
0.1
μ
F
0.1
μ
F
+
C2
C5
C1
+
+
C3
C4
+
+
0.1
μ
F
0.1
μ
F
TTINPUTS
+3V to +5V
18
SHUTDOWN
20
5K
R
1
OUT
5K
R
X
IN
R
X
OUT
OUTPUTS
R
1
IN
T
X
OUT
T
1
OUT
V
CC
1000pF
1000pF
12
V L
+3V to +5.5V
Ch1
Ch3
3
1
2
T
T
T
T
[
]
T1 IN
T1 OUT
R1 OUT
5.00V
5.00V
Ch2 5.00V M 5.00
μ
s Ch1
0V
3
1
2
T
T
T
T
[
]
T1 IN
T1 OUT
R1 OUT
Ch1
Ch3
5.00V
5.00V
Ch2 5.00V M 2.50
μ
s Ch1
0V
3
0
2
3
P
S
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