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| 型號(hào)： | SP3232EBCP-L |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 2/22頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX RS232 ESD TRUE 16PDIP |
| 產(chǎn)品變化通告： | Interface Product Discontinuation 10/May/2011 |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 類(lèi)型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | RS232 |
| 電源電壓： | 3 V ~ 5.5 V |
| 安裝類(lèi)型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 16-PDIP |
| 包裝： | 管件 |
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Exar Corporation 48720 Kato Road, Fremont CA, 94538 510-668-7017 www.exar.com
SP3222EB/SP3232EB_102_031413
Inmostcircumstances,decouplingthepower
supply can be achieved adequately using
a 0.1F bypass capacitor at C5 (refer to
figures 8 and 9)
In applications that are sensitive to power-
supply noise, decouple Vcc to ground with a
capacitor of the same value as charge-pump
capacitor C1. Physically connect bypass
capcitors as close to the IC as possible.
The charge pump operates in a discontinu-
ous mode using an internal oscillator. If the
output voltages are less than a magnitude
of 5.5V, the charge pump is enabled. If the
outputvoltages exceedamagnitudeof5.5V,
the charge pump is disabled. This oscillator
controls the four phases of the voltage shift-
ing. A description of each phase follows.
Phase 1
— V
SS charge storage — During this phase
of the clock cycle, the positive side of capaci-
tors C
1 and C2 are initially charged to VCC.
C
l
+
is then switched to GND and the charge
in C
1
–
is transferred to C
2
–
. Since C
2
+
is con-
nected to V
CC, the voltage potential across
capacitor C
2 is now 2 times VCC.
Phase 2
— V
SS transfer — Phase two of the clock
connectsthenegativeterminalofC
2 to the VSS
storagecapacitorandthepositiveterminalof
C
2 to GND. This transfers a negative gener-
ated voltage to C
3. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the volt-
age to C
3, the positive side of capacitor C1
is switched to V
CC and the negative side is
connected to GND.
Phase 3
— V
DD charge storage — The third phase of
the clock is identical to the first phase — the
charge transferred in C
1 produces –VCC in
the negative terminal of C
1, which is applied
to the negative side of capacitor C
2. Since
C
2
+
is at V
CC, the voltage potential across C2
is 2 times V
CC.
Phase 4
— V
DD transfer — The fourth phase of
the clock connects the negative terminal
of C
2 to GND, and transfers this positive
generated voltage across C
2 to C4, the
V
DD storage capacitor.
This voltage is
regulated to +5.5V. At this voltage, the in-
ternal oscillator is disabled. Simultaneous
with the transfer of the voltage to C
4, the
positive side of capacitor C
1 is switched
to V
CC and
the
negative side is con-
nected to GND, allowing the charge
pump cycle to begin again. The charge
pump cycle will continue as long as the
operational conditions for the internal
oscillator are present.
Since both V+ and V– are separately gener-
ated from V
CC, in a no–load condition V
+
and V– will be symmetrical. Older charge
pump approaches that generate V– from
V+ will show a decrease in the magnitude
of V– compared to V+ due to the inherent
inefficiencies in the design.
The clock rate for the charge pump typically
operates at greater than 250kHz. The exter-
nal capacitors can be as low as 0.1F with
a 16V breakdown voltage rating.
DESCRIPTION
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