參數(shù)資料
型號(hào)： SP3232EHCA-L/TR
廠商： Exar Corporation
文件頁(yè)數(shù)： 16/16頁(yè)
文件大小： 0K
描述： IC TXRX RS232 ESD 16SSOP
產(chǎn)品變化通告： Interface Product Discontinuation 10/May/2011
標(biāo)準(zhǔn)包裝： 1,500
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 2/2
規(guī)程： RS232
電源電壓： 3 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
Exar Corporation 48720 Kato Road, Fremont CA, 94538 510-668-7017 www.exar.com
SP3232EH_102_031413
9
of 5.5V, the charge pump is enabled. If the
outputvoltages exceedamagnitudeof5.5V,
the charge pump is disabled. This oscillator
controls the four phases of the voltage shift-
ing. A description of each phase follows.
Phase 1
— V
SS charge storage — During this phase
of the clock cycle, the positive side of capaci-
tors C
1 and C2 are initially charged to VCC.
C
l
+
is then switched to GND and the charge
in C
1
–
is transferred to C
2
–
. Since C
2
+
is con-
nected to V
CC, the voltage potential across
capacitor C
2 is now 2 times VCC.
Phase 2
— V
SS transfer — Phase two of the clock
connectsthenegativeterminalofC
2 to the VSS
storagecapacitorandthepositiveterminalof
C
2 to GND. This transfers a negative gener-
ated voltage to C
3. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the volt-
age to C
3, the positive side of capacitor C1
is switched to V
CC and the negative side is
connected to GND.
Phase 3
— V
DD charge storage — The third phase of
the clock is identical to the first phase — the
charge transferred in C
1 produces –VCC in
the negative terminal of C
1, which is applied
to the negative side of capacitor C
2. Since
C
2
+
is at V
CC, the voltage potential across C2
is 2 times V
CC.
Phase 4
— V
DD transfer — The fourth phase of
the clock connects the negative terminal
of C
2 to GND, and transfers this positive
generated voltage across C
2 to C4, the
V
DD storage capacitor.
This voltage is
regulated to +5.5V. At this voltage, the in-
ternal oscillator is disabled. Simultaneous
with the transfer of the voltage to C
4, the
positive side of capacitor C
1 is switched
to V
CC and
the
negative side is con-
nected to GND, allowing the charge
pump cycle to begin again. The charge
pump cycle will continue as long as the
operational conditions for the internal
oscillator are present.
Figure 6. SP3232EH Driver Loopback Test Circuit
Figure 8. Loopback Test results at 460kbps
T1 IN
T1 OUT
R1 OUT
Figure 7. Loopback Test results at 120kbps
SP3232EH
GND
TxIN
TxOUT
C1+
C1-
C2+
C2-
V+
V-
VCC
0.1F
+
C2
C5
C1
+
C3
C4
+
0.1F
LOGIC
INPUTS
VCC
5k
RxIN
RxOUT
LOGIC
OUTPUTS
1000pF
DESCRIPTION
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