參數(shù)資料
型號(hào): SP3238E
英文描述: Intelligent +3.0V to +5.5V RS-232 Transceivers(智能+3.0V 至 +5.5V RS-232收發(fā)器(5發(fā)3收))
中文描述: 智能3.0V至5.5V的RS - 232收發(fā)器(智能3.0V至5.5V的RS - 232接口收發(fā)器(5發(fā)3收))
文件頁(yè)數(shù): 10/20頁(yè)
文件大小: 224K
代理商: SP3238E
SP3238EDS/04
SP3238E +3.0V to +5.5V RS-232 Transceivers
10
Copyright 1999 Sipex Corporation
Since receiver input is usually from a transmission
line where long cable lengths and system
interference can degrade the signal, the inputs
have a typical hysteresis margin of 300mV. This
ensures that the receiver is virtually immune to
noisy transmission lines. Should an input be left
unconnected, an internal 5k
pulldown resistor
to ground will commit the output of the receiver
to a HIGH state.
Charge Pump
The charge pump is a
Sipex
–patented design
(U.S. 5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 5.5V
power supplies. The internal power supply
consists of a regulated dual charge pump that
provides output voltages 5.5V regardless of the
input voltage (V
) over the +3.0V to +5.5V
range. This is important to maintain compliant
RS-232 levels regardless of power supply
fluctuations.
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a magnitude of 5.5V, the
charge pump is enabled. If the output voltages
exceed a magnitude of 5.5V, the charge pump is
disabled. This oscillator controls the four phases
of the voltage shifting. A description of each
phase follows.
Phase 1
— V
charge storage — During this phase of
the clock cycle, the positive side of capacitors
C
and C
are initially charged to V
. C
l
then switched to GND and the charge in C
transferred to C
V
, the voltage potential across capacitor C
2
is
now 2 times V
CC
.
+
is
is
. Since C
+
is connected to
Phase 2
— V
transfer — Phase two of the clock
connects the negative terminal of C
to the V
SS
storage capacitor and the positive terminal of C
2
to GND. This transfers a negative generated
voltage to C
. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage to
C
, the positive side of capacitor C
is switched
to V
CC
and the negative side is connected to
GND.
Phase 3
— V
charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C
produces –V
in the negative
terminal of C
, which is applied to the negative
side of capacitor C
. Since C
voltage potential across C
2
is 2 times V
CC
.
+
is at V
CC
, the
Phase 4
— V
transfer — The fourth phase of the clock
connects the negative terminal of C
to GND,
and transfers this positive generated voltage
across C
to C
, the V
storage capacitor. This
voltage is regulated to +5.5V. At this voltage,
the internal oscillator is disabled. Simultaneous
with the transfer of the voltage to C
, the
positive side of capacitor C
is switched to V
and the negative side is connected to GND,
allowing the charge pump cycle to begin again.
The charge pump cycle will continue as long as
the operational conditions for the internal
oscillator are present.
Since both V
+
and V
are separately generated
from V
, in a no–load condition V
+
and V
will
be symmetrical. Older charge pump approaches
that generate V
from V
+
will show a decrease in
the magnitude of V
compared to V
+
due to the
inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 500kHz. The external capacitors can
be as low as 0.1
μ
F with a 16V breakdown
voltage rating.
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